


// Declare the module black box
module lab7_solution_cw (
    ce , 
    clk , 
    gateway_in , 
    fir_output 
    ); // synthesis black_box 


	// Inputs
	input ce;
	input clk;
	input [7:0] gateway_in;

	// Outputs
	output [7:0] fir_output;


//synthesis attribute box_type lab7_solution_cw "black_box"
endmodule
