spi_test Project Status (01/12/2014 - 21:45:33)
Project File: | spi2.xise | Parser Errors: | No Errors
Module Name: | spi_master | Implementation State: | Synthesized
Target Device: | xc3s400-4pq208 |

- Errors:

No Errors
Product Version: | ISE 13.2 |

- Warnings:

No Warnings
Design Goal: | Balanced |

- Routing Results:

Design Strategy: | Xilinx Default (unlocked) |

- Timing Constraints:

Environment: | System Settings |

- Final Timing Score:

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slices | 135 | 3584 | 3%
Number of Slice Flip Flops | 142 | 7168 | 1%
Number of 4 input LUTs | 212 | 7168 | 2%
Number of bonded IOBs | 98 | 141 | 69%
Number of GCLKs | 1 | 8 | 12%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Sun Jan 12 21:45:32 2014 | 0 | 0 | 4 Infos (0 new)
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | Tue Dec 17 12:44:10 2013

Date Generated: 01/12/2014 - 22:27:26