Release 13.2 - xst O.61xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.45 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.45 secs
 
--> Reading design: SERIAL_PACK.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "SERIAL_PACK.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "SERIAL_PACK"
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : SERIAL_PACK
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3607 - Unit work/SERIAL_PACK is now defined in a different file.  It was defined in "C:/Users/mazraeh/Desktop/New folder/projects/usart/SERIAL_PACK.vhd", and is now defined in "D:/tadris/fpga/eval board project/projects/usart/SERIAL_PACK.vhd".
WARNING:HDLParsers:3607 - Unit work/SERIAL_PACK/Behavioral is now defined in a different file.  It was defined in "C:/Users/mazraeh/Desktop/New folder/projects/usart/SERIAL_PACK.vhd", and is now defined in "D:/tadris/fpga/eval board project/projects/usart/SERIAL_PACK.vhd".
Compiling vhdl file "D:/tadris/fpga/eval board project/projects/usart/SERIAL_PACK.vhd" in Library work.
Architecture behavioral of Entity serial_pack is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <SERIAL_PACK> in library <work> (architecture <behavioral>) with generics.
	baud_rate = 115200
	oscillator_clk = 1843200
	parity_enable = '1'
	parity_type = '0'


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing generic Entity <SERIAL_PACK> in library <work> (Architecture <behavioral>).
	baud_rate = 115200
	oscillator_clk = 1843200
	parity_enable = '1'
	parity_type = '0'
INFO:Xst:2679 - Register <send_packet<10>> in unit <SERIAL_PACK> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <send_packet<0>> in unit <SERIAL_PACK> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <SERIAL_PACK> analyzed. Unit <SERIAL_PACK> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <SERIAL_PACK>.
    Related source file is "D:/tadris/fpga/eval board project/projects/usart/SERIAL_PACK.vhd".
WARNING:Xst:1780 - Signal <send_packet_par> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <send_packet<11>> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <send_baud_count> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rec_packet<11>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <serial_out>.
    Found 8-bit register for signal <received_data>.
    Found 1-bit register for signal <receive_flag>.
    Found 1-bit register for signal <send_flag>.
    Found 1-bit register for signal <receive_error>.
    Found 20-bit register for signal <rec_baud_counter>.
    Found 20-bit adder for signal <rec_baud_counter$addsub0000> created at line 130.
    Found 4-bit up counter for signal <rec_bit_counter>.
    Found 11-bit register for signal <rec_packet<10:0>>.
    Found 1-bit register for signal <rec_state<0>>.
    Found 1-bit xor9 for signal <receive_error$xor0000>.
    Found 20-bit register for signal <send_baud_counter>.
    Found 20-bit adder for signal <send_baud_counter$addsub0000> created at line 212.
    Found 4-bit up counter for signal <send_bit_counter>.
    Found 9-bit register for signal <send_packet<9:1>>.
    Found 1-bit xor8 for signal <send_packet_9$xor0000> created at line 185.
    Found 1-bit register for signal <send_state<0>>.
    Found 1-bit 12-to-1 multiplexer for signal <serial_out$mux0000> created at line 206.
    Summary:
	inferred   2 Counter(s).
	inferred  74 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Multiplexer(s).
	inferred   2 Xor(s).
Unit <SERIAL_PACK> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 20-bit adder                                          : 2
# Counters                                             : 2
 4-bit up counter                                      : 2
# Registers                                            : 29
 1-bit register                                        : 26
 20-bit register                                       : 2
 8-bit register                                        : 1
# Multiplexers                                         : 1
 1-bit 12-to-1 multiplexer                             : 1
# Xors                                                 : 2
 1-bit xor8                                            : 1
 1-bit xor9                                            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 20-bit adder                                          : 2
# Counters                                             : 2
 4-bit up counter                                      : 2
# Registers                                            : 74
 Flip-Flops                                            : 74
# Multiplexers                                         : 1
 1-bit 12-to-1 multiplexer                             : 1
# Xors                                                 : 2
 1-bit xor8                                            : 1
 1-bit xor9                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <SERIAL_PACK> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block SERIAL_PACK, actual ratio is 2.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 82
 Flip-Flops                                            : 82

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : SERIAL_PACK.ngr
Top Level Output File Name         : SERIAL_PACK
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 24

Cell Usage :
# BELS                             : 246
#      GND                         : 1
#      INV                         : 6
#      LUT1                        : 38
#      LUT2                        : 9
#      LUT2_L                      : 4
#      LUT3                        : 50
#      LUT3_D                      : 2
#      LUT4                        : 38
#      LUT4_D                      : 7
#      LUT4_L                      : 3
#      MUXCY                       : 43
#      MUXF5                       : 3
#      MUXF6                       : 1
#      VCC                         : 1
#      XORCY                       : 40
# FlipFlops/Latches                : 82
#      FD                          : 21
#      FDE                         : 31
#      FDR                         : 20
#      FDRE                        : 9
#      FDS                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 23
#      IBUF                        : 11
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                       91  out of   3584     2%  
 Number of Slice Flip Flops:             82  out of   7168     1%  
 Number of 4 input LUTs:                157  out of   7168     2%  
 Number of IOs:                          24
 Number of bonded IOBs:                  24  out of    141    17%  
 Number of GCLKs:                         1  out of      8    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 82    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.345ns (Maximum Frequency: 119.832MHz)
   Minimum input arrival time before clock: 4.696ns
   Maximum output required time after clock: 7.241ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 8.345ns (frequency: 119.832MHz)
  Total number of paths / destination ports: 2215 / 131
-------------------------------------------------------------------------
Delay:               8.345ns (Levels of Logic = 4)
  Source:            send_baud_counter_14 (FF)
  Destination:       send_flag (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: send_baud_counter_14 to send_flag
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.720   1.216  send_baud_counter_14 (send_baud_counter_14)
     LUT4:I0->O            2   0.551   1.072  serial_out_not0001125 (serial_out_not0001125)
     LUT4:I1->O            1   0.551   0.827  serial_out_not0001176_1 (serial_out_not0001176)
     LUT4_D:I3->O          2   0.551   0.903  send_bit_counter_and000011 (N12)
     LUT4:I3->O            1   0.551   0.801  send_flag_not00011 (send_flag_not0001)
     FDE:CE                    0.602          send_flag
    ----------------------------------------
    Total                      8.345ns (3.526ns logic, 4.819ns route)
                                       (42.3% logic, 57.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 46 / 33
-------------------------------------------------------------------------
Offset:              4.696ns (Levels of Logic = 4)
  Source:            serial_in (PAD)
  Destination:       rec_state_0 (FF)
  Destination Clock: clk rising

  Data Path: serial_in to rec_state_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            15   0.821   1.383  serial_in_IBUF (serial_in_IBUF)
     LUT4:I1->O            1   0.551   0.000  rec_state_0_mux000011_SW4_G (N69)
     MUXF5:I1->O           1   0.360   0.827  rec_state_0_mux000011_SW4 (N66)
     LUT4:I3->O            1   0.551   0.000  rec_state_0_mux00002 (rec_state_0_mux0000)
     FD:D                      0.203          rec_state_0
    ----------------------------------------
    Total                      4.696ns (2.486ns logic, 2.210ns route)
                                       (52.9% logic, 47.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 12 / 12
-------------------------------------------------------------------------
Offset:              7.241ns (Levels of Logic = 1)
  Source:            send_flag (FF)
  Destination:       send_flag (PAD)
  Source Clock:      clk rising

  Data Path: send_flag to send_flag
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.720   0.877  send_flag (send_flag_OBUF)
     OBUF:I->O                 5.644          send_flag_OBUF (send_flag)
    ----------------------------------------
    Total                      7.241ns (6.364ns logic, 0.877ns route)
                                       (87.9% logic, 12.1% route)

=========================================================================


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.34 secs
 
--> 

Total memory usage is 251052 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    6 (   0 filtered)
Number of infos    :    2 (   0 filtered)

