{
  'attributes' => {
    'HDLCodeGenStatus' => 0,
    'HDL_PATH' => 'C:/Users/mazraeh/Desktop/lab7/solution',
    'TEMP' => 'C:/Users/mazraeh/AppData/Local/Temp',
    'TMP' => 'C:/Users/mazraeh/AppData/Local/Temp',
    'Temp' => 'C:/Users/mazraeh/AppData/Local/Temp',
    'Tmp' => 'C:/Users/mazraeh/AppData/Local/Temp',
    'base_system_period_hardware' => 10,
    'base_system_period_simulink' => '1.11111111111111e-006',
    'block_icon_display' => 'Default',
    'block_type' => 'sysgen',
    'block_version' => 8.2,
    'ce_clr' => 0,
    'clock_domain' => 'default',
    'clock_loc' => '',
    'clock_wrapper' => 'Clock Enables',
    'compilation' => 'HDL Netlist',
    'compilation_lut' => {
      'keys' => [
        'HDL Netlist',
        'Timing Analysis',
        'Bitstream',
      ],
      'values' => [
        'target1',
        'target2',
        'target3',
      ],
    },
    'compilation_target' => 'HDL Netlist',
    'core_generation' => 1,
    'core_generation_sgadvanced' => '',
    'core_is_deployed' => 0,
    'coregen_core_generation_tmpdir' => 'C:/Users/mazraeh/AppData/Local/Temp/sysgentmp-mazraeh/cg_wk/ce1787653e96f4c65',
    'coregen_part_family' => 'spartan3',
    'createTestbench' => 1,
    'create_interface_document' => 'off',
    'dbl_ovrd' => -1,
    'dbl_ovrd_sgadvanced' => '',
    'dcm_info' => {
    },
    'dcm_input_clock_period' => 100,
    'deprecated_control' => 'off',
    'deprecated_control_sgadvanced' => '',
    'design' => 'lab7_solution',
    'designFile' => 'lab7_solution.vhd',
    'design_full_path' => 'C:\\Users\\mazraeh\\Desktop\\lab7\\solution\\lab7_solution.mdl',
    'device' => 'xc3s400-4pq208',
    'device_speed' => -4,
    'directory' => 'C:/Users/mazraeh/Desktop/lab7/solution',
    'dsp_cache_root_path' => 'C:/Users/mazraeh/AppData/Local/Temp/sysgentmp-mazraeh',
    'entityNamingInstrs' => {
      'nameMap' => undef,
      'namesAlreadyUsed' => undef,
    },
    'eval_field' => 0,
    'fileAttributes' => {
      'fir_compiler_v5_0.mif' => {
        'producer' => 'coregen',
      },
      'fr_cmplr_v5_0_e9beb8b22d627e43.mif' => {
        'producer' => 'coregen',
      },
      'fr_cmplr_v5_0_e9beb8b22d627e43.ngc' => {
        'producer' => 'coregen',
      },
      'fr_cmplr_v5_0_e9beb8b22d627e43COEFF_auto0_0.mif' => {
        'producer' => 'coregen',
      },
      'fr_cmplr_v5_0_e9beb8b22d627e43filt_decode_rom.mif' => {
        'producer' => 'coregen',
      },
    },
    'files' => [
      'fir_compiler_v5_0.mif',
      'fr_cmplr_v5_0_e9beb8b22d627e43.mif',
      'fr_cmplr_v5_0_e9beb8b22d627e43.ngc',
      'fr_cmplr_v5_0_e9beb8b22d627e43COEFF_auto0_0.mif',
      'fr_cmplr_v5_0_e9beb8b22d627e43filt_decode_rom.mif',
      'xlpersistentdff.ngc',
      'synopsis',
      'lab7_solution.vhd',
    ],
    'fxdptinstalled' => 1,
    'generateUsing71FrontEnd' => 1,
    'generating_island_subsystem_handle' => 2070.00012207031,
    'generating_subsystem_handle' => 2070.00012207031,
    'generation_directory' => 'C:/Users/mazraeh/Desktop/lab7/solution',
    'has_advanced_control' => 0,
    'hdlDir' => 'C:/Xilinx/13.2/ISE_DS/ISE/sysgen/hdl',
    'hdlKind' => 'vhdl',
    'hdl_path' => 'C:/Users/mazraeh/Desktop/lab7/solution',
    'incr_netlist' => 'off',
    'incr_netlist_sgadvanced' => '',
    'infoedit' => ' System Generator',
    'isdeployed' => 0,
    'ise_version' => '13.2i',
    'master_sysgen_token_handle' => 2071.00012207031,
    'matlab' => 'C:/Program Files/MATLAB/R2011a',
    'matlab_fixedpoint' => 1,
    'mdlHandle' => 2070.00012207031,
    'mdlPath' => 'C:/Users/mazraeh/Desktop/lab7/solution/lab7_solution.mdl',
    'modelDiagnostics' => [
      {
        'count' => 53,
        'isMask' => 0,
        'type' => 'lab7_solution Total blocks',
      },
      {
        'count' => 1,
        'isMask' => 0,
        'type' => 'DataTypeConversion',
      },
      {
        'count' => 2,
        'isMask' => 0,
        'type' => 'DiscretePulseGenerator',
      },
      {
        'count' => 1,
        'isMask' => 0,
        'type' => 'DotProduct',
      },
      {
        'count' => 8,
        'isMask' => 0,
        'type' => 'Inport',
      },
      {
        'count' => 1,
        'isMask' => 0,
        'type' => 'M-S-Function',
      },
      {
        'count' => 2,
        'isMask' => 0,
        'type' => 'Math',
      },
      {
        'count' => 1,
        'isMask' => 0,
        'type' => 'Mux',
      },
      {
        'count' => 7,
        'isMask' => 0,
        'type' => 'Outport',
      },
      {
        'count' => 2,
        'isMask' => 0,
        'type' => 'Probe',
      },
      {
        'count' => 2,
        'isMask' => 0,
        'type' => 'Product',
      },
      {
        'count' => 13,
        'isMask' => 0,
        'type' => 'S-Function',
      },
      {
        'count' => 1,
        'isMask' => 0,
        'type' => 'Selector',
      },
      {
        'count' => 9,
        'isMask' => 0,
        'type' => 'SubSystem',
      },
      {
        'count' => 3,
        'isMask' => 0,
        'type' => 'Terminator',
      },
      {
        'count' => 4,
        'isMask' => 1,
        'type' => 'Check Signal Attributes',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Digital Filter',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'FFT',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Frame Scope',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Magnitude FFT',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Periodogram',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Replaceable Contents',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Spectrum Scope',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Submatrix',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Window Function',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Xilinx Copyright Notice Block',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Xilinx FDATool Interface Block',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Xilinx FIR Compiler 5.0 Block',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Xilinx Gateway In Block',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Xilinx Gateway Out Block',
      },
      {
        'count' => 2,
        'isMask' => 1,
        'type' => 'Xilinx Register Block',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Xilinx System Generator Block',
      },
    ],
    'model_globals_initialized' => 1,
    'model_path' => 'C:/Users/mazraeh/Desktop/lab7/solution/lab7_solution.mdl',
    'myxilinx' => 'C:/Xilinx/13.2/ISE_DS/ISE',
    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
    'ngc_files' => [
      'xlpersistentdff.ngc',
    ],
    'num_sim_cycles' => 90000,
    'package' => 'pq208',
    'part' => 'xc3s400',
    'partFamily' => 'spartan3',
    'port_data_types_enabled' => 0,
    'preserve_hierarchy' => 0,
    'proj_type' => 'Project Navigator',
    'run_coregen' => 'off',
    'run_coregen_sgadvanced' => '',
    'sample_time_colors_enabled' => 0,
    'sampletimecolors' => 0,
    'sg_blockgui_xml' => '<!--  *  Copyright (c) 2005, Xilinx, Inc.  All Rights Reserved.            --><!--  *  Reproduction or reuse, in any form, without the explicit written  --><!--  *  consent of Xilinx, Inc., is strictly prohibited.                  --><sysgenblock has_userdata="true" tag="genX" block_type="sysgen" simulinkname=" System Generator" >
 <icon width="51" bg_color="beige" height="50" caption_format="System\\nGenerator" wmark_color="red" />
 <callbacks DeleteFcn="xlSysgenGUI(\'delete\', gcs, gcbh);" OpenFcn="xlSysgenGUI(\'startup\',gcs,gcbh)" ModelCloseFcn="xlSysgenGUI(\'Close\',gcs,gcbh)" PostSaveFcn="xlSysgenGUI(\'Save\')" />
 <libraries>
  <library name="xbsIndex" />
  <library name="xbsBasic" />
  <library name="xbsTools" />
 </libraries>
 <subsystem_model file="system_generator_subsystem.mdl" />
 <blockgui label="Xilinx System Generator" >
  <editbox evaluate="false" multi_line="true" name="infoedit" read_only="true" default=" System Generator" />
  <editbox evaluate="false" name="xilinxfamily" default="Virtex4" label="Xilinx family" />
  <editbox evaluate="false" name="part" default="xc4vsx35" label="Part" />
  <editbox evaluate="false" name="speed" default="-10" label="Speed" />
  <editbox evaluate="false" name="package" default="ff668" label="Package" />
  <listbox evaluate="true" name="synthesis_tool" default="XST" label="Synthesis tool" >
   <item value="Spectrum" />
   <item value="Synplify" />
   <item value="Synplify Pro" />
   <item value="XST" />
   <item value="Precision" />
  </listbox>
  <editbox evaluate="false" name="directory" default="./netlist" label="Target directory" />
  <checkbox evaluate="true" name="testbench" default="off" label="Testbench" />
  <editbox evaluate="true" name="simulink_period" default="1" label="Simulink period" />
  <editbox evaluate="true" name="sysclk_period" default="10" label="System clock period" />
  <checkbox evaluate="true" name="incr_netlist" default="off" label="Incremental netlisting" />
  <listbox evaluate="true" name="trim_vbits" default="Everywhere in SubSystem" label="Trim valid bits" >
   <item value="According to Block Masks" />
   <item value="Everywhere in SubSystem" />
   <item value="No Where in SubSystem" />
  </listbox>
  <listbox evaluate="true" name="dbl_ovrd" default="According to Block Masks" label="Override with doubles" >
   <item value="According to Block Masks" />
   <item value="Everywhere in SubSystem" />
   <item value="No Where in SubSystem" />
  </listbox>
  <listbox evaluate="true" name="core_generation" default="According to Block Masks" label="Generate cores" >
   <item value="According to Block Masks" />
   <item value="Everywhere Available" />
   <item value="Not Needed - Already Generated" />
  </listbox>
  <checkbox evaluate="true" name="run_coregen" default="off" label="Run CoreGen" />
  <checkbox evaluate="true" name="deprecated_control" default="off" label="Show deprecated controls" />
  <hiddenvar evaluate="true" name="eval_field" default="0" />
 </blockgui>
</sysgenblock>
',
    'sg_icon_stat' => '51,50,-1,-1,red,beige,0,07734',
    'sg_list_contents' => '',
    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
patch([0 51 51 0 ],[0 0 50 50 ],[0.93 0.92 0.86]);
patch([12 4 16 4 12 25 29 33 47 36 25 17 29 17 25 36 47 33 29 25 12 ],[5 13 25 37 45 45 41 45 45 34 45 37 25 13 5 16 5 5 9 5 5 ],[0.6 0.2 0.25]);
plot([0 0 51 51 0 ],[0 50 50 0 0 ]);
fprintf(\'\',\'COMMENT: end icon graphics\');
fprintf(\'\',\'COMMENT: begin icon text\');
fprintf(\'\',\'COMMENT: end icon text\');
',
    'sg_version' => '',
    'sggui_pos' => '-1,-1,-1,-1',
    'simulation_island_subsystem_handle' => 2070.00012207031,
    'simulinkName' => 'parking_lot',
    'simulink_accelerator_running' => 0,
    'simulink_debugger_running' => 0,
    'simulink_period' => '1.11111111111111e-006',
    'speed' => -4,
    'synthesisTool' => 'XST',
    'synthesis_language' => 'vhdl',
    'synthesis_tool' => 'XST',
    'synthesis_tool_sgadvanced' => '',
    'sysclk_period' => 10,
    'sysgen' => 'C:/Xilinx/13.2/ISE_DS/ISE/sysgen',
    'sysgenRoot' => 'C:/Xilinx/13.2/ISE_DS/ISE/sysgen',
    'sysgenTokenSettings' => {
      'base_system_period_hardware' => 10,
      'base_system_period_simulink' => '1.11111111111111e-006',
      'block_icon_display' => 'Default',
      'block_type' => 'sysgen',
      'block_version' => 8.2,
      'ce_clr' => 0,
      'clock_loc' => '',
      'clock_wrapper' => 'Clock Enables',
      'compilation' => 'HDL Netlist',
      'compilation_lut' => {
        'keys' => [
          'HDL Netlist',
          'Timing Analysis',
          'Bitstream',
        ],
        'values' => [
          'target1',
          'target2',
          'target3',
        ],
      },
      'core_generation' => 1,
      'core_generation_sgadvanced' => '',
      'coregen_part_family' => 'spartan3',
      'create_interface_document' => 'off',
      'dbl_ovrd' => -1,
      'dbl_ovrd_sgadvanced' => '',
      'dcm_input_clock_period' => 100,
      'deprecated_control' => 'off',
      'deprecated_control_sgadvanced' => '',
      'directory' => 'C:/Users/mazraeh/Desktop/lab7/solution',
      'eval_field' => 0,
      'has_advanced_control' => 0,
      'incr_netlist' => 'off',
      'incr_netlist_sgadvanced' => '',
      'infoedit' => ' System Generator',
      'master_sysgen_token_handle' => 2071.00012207031,
      'package' => 'pq208',
      'part' => 'xc3s400',
      'preserve_hierarchy' => 0,
      'proj_type' => 'Project Navigator',
      'run_coregen' => 'off',
      'run_coregen_sgadvanced' => '',
      'sg_blockgui_xml' => '<!--  *  Copyright (c) 2005, Xilinx, Inc.  All Rights Reserved.            --><!--  *  Reproduction or reuse, in any form, without the explicit written  --><!--  *  consent of Xilinx, Inc., is strictly prohibited.                  --><sysgenblock has_userdata="true" tag="genX" block_type="sysgen" simulinkname=" System Generator" >
 <icon width="51" bg_color="beige" height="50" caption_format="System\\nGenerator" wmark_color="red" />
 <callbacks DeleteFcn="xlSysgenGUI(\'delete\', gcs, gcbh);" OpenFcn="xlSysgenGUI(\'startup\',gcs,gcbh)" ModelCloseFcn="xlSysgenGUI(\'Close\',gcs,gcbh)" PostSaveFcn="xlSysgenGUI(\'Save\')" />
 <libraries>
  <library name="xbsIndex" />
  <library name="xbsBasic" />
  <library name="xbsTools" />
 </libraries>
 <subsystem_model file="system_generator_subsystem.mdl" />
 <blockgui label="Xilinx System Generator" >
  <editbox evaluate="false" multi_line="true" name="infoedit" read_only="true" default=" System Generator" />
  <editbox evaluate="false" name="xilinxfamily" default="Virtex4" label="Xilinx family" />
  <editbox evaluate="false" name="part" default="xc4vsx35" label="Part" />
  <editbox evaluate="false" name="speed" default="-10" label="Speed" />
  <editbox evaluate="false" name="package" default="ff668" label="Package" />
  <listbox evaluate="true" name="synthesis_tool" default="XST" label="Synthesis tool" >
   <item value="Spectrum" />
   <item value="Synplify" />
   <item value="Synplify Pro" />
   <item value="XST" />
   <item value="Precision" />
  </listbox>
  <editbox evaluate="false" name="directory" default="./netlist" label="Target directory" />
  <checkbox evaluate="true" name="testbench" default="off" label="Testbench" />
  <editbox evaluate="true" name="simulink_period" default="1" label="Simulink period" />
  <editbox evaluate="true" name="sysclk_period" default="10" label="System clock period" />
  <checkbox evaluate="true" name="incr_netlist" default="off" label="Incremental netlisting" />
  <listbox evaluate="true" name="trim_vbits" default="Everywhere in SubSystem" label="Trim valid bits" >
   <item value="According to Block Masks" />
   <item value="Everywhere in SubSystem" />
   <item value="No Where in SubSystem" />
  </listbox>
  <listbox evaluate="true" name="dbl_ovrd" default="According to Block Masks" label="Override with doubles" >
   <item value="According to Block Masks" />
   <item value="Everywhere in SubSystem" />
   <item value="No Where in SubSystem" />
  </listbox>
  <listbox evaluate="true" name="core_generation" default="According to Block Masks" label="Generate cores" >
   <item value="According to Block Masks" />
   <item value="Everywhere Available" />
   <item value="Not Needed - Already Generated" />
  </listbox>
  <checkbox evaluate="true" name="run_coregen" default="off" label="Run CoreGen" />
  <checkbox evaluate="true" name="deprecated_control" default="off" label="Show deprecated controls" />
  <hiddenvar evaluate="true" name="eval_field" default="0" />
 </blockgui>
</sysgenblock>
',
      'sg_icon_stat' => '51,50,-1,-1,red,beige,0,07734',
      'sg_list_contents' => '',
      'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
patch([0 51 51 0 ],[0 0 50 50 ],[0.93 0.92 0.86]);
patch([12 4 16 4 12 25 29 33 47 36 25 17 29 17 25 36 47 33 29 25 12 ],[5 13 25 37 45 45 41 45 45 34 45 37 25 13 5 16 5 5 9 5 5 ],[0.6 0.2 0.25]);
plot([0 0 51 51 0 ],[0 50 50 0 0 ]);
fprintf(\'\',\'COMMENT: end icon graphics\');
fprintf(\'\',\'COMMENT: begin icon text\');
fprintf(\'\',\'COMMENT: end icon text\');
',
      'sggui_pos' => '-1,-1,-1,-1',
      'simulation_island_subsystem_handle' => 2070.00012207031,
      'simulink_period' => '1.11111111111111e-006',
      'speed' => -4,
      'synthesis_language' => 'vhdl',
      'synthesis_tool' => 'XST',
      'synthesis_tool_sgadvanced' => '',
      'sysclk_period' => 10,
      'testbench' => 1,
      'testbench_sgadvanced' => '',
      'trim_vbits' => 1,
      'trim_vbits_sgadvanced' => '',
      'xilinx_device' => 'xc3s400-4pq208',
      'xilinxfamily' => 'spartan3',
    },
    'sysgen_Root' => 'C:/Xilinx/13.2/ISE_DS/ISE/sysgen',
    'systemClockPeriod' => 10,
    'tempdir' => 'C:/Users/mazraeh/AppData/Local/Temp',
    'testbench' => 1,
    'testbench_sgadvanced' => '',
    'tmpDir' => 'C:/Users/mazraeh/Desktop/lab7/solution/sysgen',
    'trim_vbits' => 1,
    'trim_vbits_sgadvanced' => '',
    'use_strict_names' => 1,
    'user_tips_enabled' => 0,
    'usertemp' => 'C:/Users/mazraeh/AppData/Local/Temp/sysgentmp-mazraeh',
    'using71Netlister' => 1,
    'verilog_files' => [
      'conv_pkg.v',
      'synth_reg.v',
      'synth_reg_w_init.v',
      'convert_type.v',
    ],
    'version' => '',
    'vhdl_files' => [
      'conv_pkg.vhd',
      'synth_reg.vhd',
      'synth_reg_w_init.vhd',
    ],
    'vsimtime' => '990275.000000 ns',
    'xilinx' => 'C:/Xilinx/13.2/ISE_DS/ISE',
    'xilinx_device' => 'xc3s400-4pq208',
    'xilinx_family' => 'spartan3',
    'xilinx_package' => 'pq208',
    'xilinx_part' => 'xc3s400',
    'xilinxdevice' => 'xc3s400-4pq208',
    'xilinxfamily' => 'spartan3',
    'xilinxpart' => 'xc3s400',
  },
  'entityName' => '',
  'nets' => {
    'ce_1_sg_x0' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'ce_450_sg_x0' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'ce_logic_450_sg_x0' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'clk_1_sg_x0' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'clk_450_sg_x0' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'fir_output_net' => {
      'hdlType' => 'std_logic_vector(7 downto 0)',
      'width' => 8,
    },
    'gateway_in_net' => {
      'hdlType' => 'std_logic_vector(7 downto 0)',
      'width' => 8,
    },
  },
  'subblocks' => {
    'default_clock_driver' => {
      'connections' => {
        'ce_1' => 'ce_1_sg_x0',
        'ce_450' => 'ce_450_sg_x0',
        'ce_logic_450' => 'ce_logic_450_sg_x0',
        'clk_1' => 'clk_1_sg_x0',
        'clk_450' => 'clk_450_sg_x0',
      },
      'entity' => {
        'attributes' => {
          'domain' => 'default',
          'isClkDriver' => 1,
        },
        'entityName' => 'default_clock_driver',
        'ports' => {
          'ce_1' => {
            'attributes' => {
              'domain' => 'default',
              'group' => 1,
              'isCe' => 1,
              'period' => 1,
              'type' => 'logic',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'ce_450' => {
            'attributes' => {
              'domain' => 'default',
              'group' => 1,
              'isCe' => 1,
              'period' => 450,
              'type' => 'logic',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'ce_logic_450' => {
            'attributes' => {
              'domain' => 'default',
              'group' => 1,
              'isCeLogic' => 1,
              'period' => 450,
              'type' => 'logic',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'clk_1' => {
            'attributes' => {
              'domain' => 'default',
              'group' => 1,
              'isClk' => 1,
              'period' => 1,
              'type' => 'logic',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'clk_450' => {
            'attributes' => {
              'domain' => 'default',
              'group' => 1,
              'isClk' => 1,
              'period' => 450,
              'type' => 'logic',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
        },
      },
      'entityName' => 'default_clock_driver',
    },
    'fir_output' => {
      'connections' => {
        'fir_output' => 'fir_output_net',
      },
      'entity' => {
        'attributes' => {
          'isGateway' => 1,
          'is_floating_block' => 1,
        },
        'entityName' => 'fir_output',
        'ports' => {
          'fir_output' => {
            'attributes' => {
              'bin_pt' => 0,
              'inputFile' => 'lab7_solution_fir_output.dat',
              'is_floating_block' => 1,
              'is_gateway_port' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 450,
              'port_id' => 0,
              'simulinkName' => 'lab7_solution/FIR Output/FIR Output',
              'source_block' => 'lab7_solution/FIR Output',
              'timingConstraint' => 'none',
              'type' => 'Fix_8_0',
            },
            'direction' => 'in',
            'hdlType' => 'std_logic_vector(7 downto 0)',
            'width' => 8,
          },
        },
      },
      'entityName' => 'fir_output',
    },
    'gateway_in' => {
      'connections' => {
        'gateway_in' => 'gateway_in_net',
      },
      'entity' => {
        'attributes' => {
          'isGateway' => 1,
          'is_floating_block' => 1,
        },
        'entityName' => 'gateway_in',
        'ports' => {
          'gateway_in' => {
            'attributes' => {
              'bin_pt' => 7,
              'inputFile' => 'lab7_solution_gateway_in.dat',
              'is_floating_block' => 1,
              'is_gateway_port' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 450,
              'port_id' => 0,
              'simulinkName' => 'lab7_solution/Gateway In/Gateway In',
              'source_block' => 'lab7_solution/Gateway In',
              'timingConstraint' => 'none',
              'type' => 'Fix_8_7',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic_vector(7 downto 0)',
            'width' => 8,
          },
        },
      },
      'entityName' => 'gateway_in',
    },
    'lab7_solution' => {
      'connections' => {
        'ce_1' => 'ce_1_sg_x0',
        'ce_450' => 'ce_450_sg_x0',
        'ce_logic_450' => 'ce_logic_450_sg_x0',
        'clk_1' => 'clk_1_sg_x0',
        'clk_450' => 'clk_450_sg_x0',
        'fir_output' => 'fir_output_net',
        'gateway_in' => 'gateway_in_net',
      },
      'entity' => {
        'attributes' => {
          'entityAlreadyNetlisted' => 1,
          'hdlKind' => 'vhdl',
          'isDesign' => 1,
          'simulinkName' => 'lab7_solution',
        },
        'entityName' => 'lab7_solution',
        'ports' => {
          'ce_1' => {
            'attributes' => {
              'domain' => '',
              'group' => 1,
              'isCe' => 1,
              'is_subsys_port' => 1,
              'period' => 1,
              'subsys_port_index' => 0,
              'type' => 'logic',
            },
            'direction' => 'in',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'ce_450' => {
            'attributes' => {
              'domain' => '',
              'group' => 1,
              'isCe' => 1,
              'is_subsys_port' => 1,
              'period' => 450,
              'subsys_port_index' => 1,
              'type' => 'logic',
            },
            'direction' => 'in',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'ce_logic_450' => {
            'attributes' => {
              'domain' => '',
              'group' => 1,
              'isCe' => 1,
              'is_subsys_port' => 1,
              'period' => 450,
              'subsys_port_index' => 1,
              'type' => 'logic',
            },
            'direction' => 'in',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'clk_1' => {
            'attributes' => {
              'domain' => '',
              'group' => 1,
              'isClk' => 1,
              'is_subsys_port' => 1,
              'period' => 1,
              'subsys_port_index' => 0,
              'type' => 'logic',
            },
            'direction' => 'in',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'clk_450' => {
            'attributes' => {
              'domain' => '',
              'group' => 1,
              'isClk' => 1,
              'is_subsys_port' => 1,
              'period' => 450,
              'subsys_port_index' => 1,
              'type' => 'logic',
            },
            'direction' => 'in',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'fir_output' => {
            'attributes' => {
              'bin_pt' => 0,
              'inputFile' => 'lab7_solution_fir_output.dat',
              'is_floating_block' => 1,
              'is_gateway_port' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 450,
              'port_id' => 0,
              'simulinkName' => 'lab7_solution/FIR Output',
              'source_block' => 'lab7_solution',
              'timingConstraint' => 'none',
              'type' => 'Fix_8_0',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic_vector(7 downto 0)',
            'width' => 8,
          },
          'gateway_in' => {
            'attributes' => {
              'bin_pt' => 7,
              'inputFile' => 'lab7_solution_gateway_in.dat',
              'is_floating_block' => 1,
              'is_gateway_port' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 450,
              'port_id' => 0,
              'simulinkName' => 'lab7_solution/Gateway In',
              'source_block' => 'lab7_solution',
              'timingConstraint' => 'none',
              'type' => 'Fix_8_7',
            },
            'direction' => 'in',
            'hdlType' => 'std_logic_vector(7 downto 0)',
            'width' => 8,
          },
        },
      },
      'entityName' => 'lab7_solution',
    },
  },
}
