test Project Status (01/22/2017 - 18:47:55)
Project File: | lcd3.xise | Parser Errors: | No Errors
Module Name: | test | Implementation State: | Mapped
Target Device: | xc3s400-4pq208 |

- Errors:

No Errors
Product Version: | ISE 13.2 |

- Warnings:

2 Warnings (0 new)
Design Goal: | Balanced |

- Routing Results:

Design Strategy: | Xilinx Default (unlocked) |

- Timing Constraints:

Environment: | System Settings |

- Final Timing Score:

Device Utilization Summary | [-]
Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Flip Flops | 27 | 7,168 | 1% |
Number of 4 input LUTs | 73 | 7,168 | 1% |
Number of occupied Slices | 44 | 3,584 | 1% |
Number of Slices containing only related logic | 44 | 44 | 100% |
Number of Slices containing unrelated logic | 0 | 44 | 0% |
Total Number of 4 input LUTs | 85 | 7,168 | 1% |
Number used as logic | 73 |  |  |
Number used as a route-thru | 12 |  |  |
Number of bonded IOBs | 12 | 141 | 8% |
Number of BUFGMUXs | 1 | 8 | 12% |
Average Fanout of Non-Clock Nets | 3.57 |  |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Sun Jan 22 18:47:23 2017 | 0 | 2 Warnings (0 new) | 2 Infos (0 new)
Translation Report | Current | Sun Jan 22 18:47:28 2017 | 0 | 0 | 0
Map Report | Current | Sun Jan 22 18:47:32 2017 | 0 | 0 | 4 Infos (0 new)
Place and Route Report | Out of Date | Sun Jan 22 18:10:20 2017 | 0 | 0 | 2 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Sun Jan 22 18:47:43 2017 | 0 | 0 | 5 Infos (0 new)
Bitgen Report | Current | Sun Jan 22 18:47:49 2017 | 0 | 0 | 1 Info (0 new)

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | Sun Jan 22 18:47:50 2017
WebTalk Log File | Current | Sun Jan 22 18:47:55 2017

Date Generated: 01/22/2017 - 18:47:56