Release 13.2 - xst O.61xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Reading design: ps2_test.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "ps2_test.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "ps2_test"
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : ps2_test
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Users/mazraeh/Desktop/fpga project/ps2/test.vhd" in Library work.
Architecture alse_rtl of Entity ps2_ctrl is up to date.
Compiling vhdl file "C:/Users/mazraeh/Desktop/fpga project/ps2/ps2_test.vhd" in Library work.
Entity <ps2_test> compiled.
Entity <ps2_test> (Architecture <behavioral>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <ps2_test> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <PS2_Ctrl> in library <work> (architecture <alse_rtl>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ps2_test> in library <work> (Architecture <behavioral>).
INFO:Xst:2679 - Register <LCD_RW> in unit <ps2_test> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <ps2_test> analyzed. Unit <ps2_test> generated.

Analyzing Entity <PS2_Ctrl> in library <work> (Architecture <alse_rtl>).
Entity <PS2_Ctrl> analyzed. Unit <PS2_Ctrl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <PS2_Ctrl>.
    Related source file is "C:/Users/mazraeh/Desktop/fpga project/ps2/test.vhd".
    Found 1-bit register for signal <Scan_Err>.
    Found 8-bit register for signal <Scan_Code>.
    Found 4-bit up counter for signal <Bit_Cnt>.
    Found 1-bit register for signal <Fall_Clk>.
    Found 8-bit register for signal <Filter>.
    Found 1-bit register for signal <Parity>.
    Found 1-bit xor2 for signal <Parity$xor0000> created at line 112.
    Found 1-bit register for signal <PS2_Clk_f>.
    Found 1-bit register for signal <PS2_Datr>.
    Found 9-bit register for signal <S_Reg>.
    Found 4-bit comparator greatequal for signal <S_Reg$cmp_ge0000> created at line 101.
    Found 1-bit register for signal <Scan_DAVi>.
    Found 1-bit register for signal <State<0>>.
    Found 4-bit comparator less for signal <State_0$cmp_lt0000> created at line 101.
    Summary:
	inferred   1 Counter(s).
	inferred  32 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <PS2_Ctrl> synthesized.


Synthesizing Unit <ps2_test>.
    Related source file is "C:/Users/mazraeh/Desktop/fpga project/ps2/ps2_test.vhd".
WARNING:Xst:1780 - Signal <data_rdy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_0> for signal <state0>.
    -----------------------------------------------------------------------
    | States             | 16                                             |
    | Transitions        | 32                                             |
    | Inputs             | 2                                              |
    | Outputs            | 16                                             |
    | Clock              | clk                       (rising_edge)        |
    | Power Up State     | 01011                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 5                                              |
    | Inputs             | 2                                              |
    | Outputs            | 4                                              |
    | Clock              | clk                       (rising_edge)        |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <led>.
    Found 8-bit register for signal <SF_D>.
    Found 1-bit register for signal <LCD_E>.
    Found 1-bit register for signal <LCD_RS>.
    Found 8-bit register for signal <char1>.
    Found 4-bit comparator less for signal <char1$cmp_lt0000> created at line 125.
    Found 8-bit adder for signal <char1$mux0001>.
    Found 8-bit register for signal <char2>.
    Found 4-bit comparator less for signal <char2$cmp_lt0000> created at line 135.
    Found 8-bit adder for signal <char2$mux0001>.
    Found 11-bit register for signal <cnt>.
    Found 11-bit adder for signal <cnt$share0000> created at line 174.
    Found 1-bit register for signal <DoRead>.
    Found 1-bit register for signal <Reset>.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred  47 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <ps2_test> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 3
 11-bit adder                                          : 1
 8-bit adder                                           : 2
# Counters                                             : 1
 4-bit up counter                                      : 1
# Registers                                            : 19
 1-bit register                                        : 11
 11-bit register                                       : 1
 8-bit register                                        : 6
 9-bit register                                        : 1
# Comparators                                          : 4
 4-bit comparator greatequal                           : 1
 4-bit comparator less                                 : 3
# Xors                                                 : 1
 1-bit xor2                                            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <state/FSM> on signal <state[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 10
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <state0/FSM> on signal <state0[1:4]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 01011 | 0000
 01100 | 0001
 01101 | 0010
 01110 | 0011
 01111 | 0100
 10000 | 0101
 10001 | 0110
 10010 | 0111
 10011 | 1000
 10100 | 1001
 10101 | 1010
 10110 | 1011
 10111 | 1100
 11000 | 1101
 11001 | 1110
 11010 | 1111
-------------------

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 2
# Adders/Subtractors                                   : 3
 11-bit adder                                          : 1
 8-bit adder                                           : 2
# Counters                                             : 1
 4-bit up counter                                      : 1
# Registers                                            : 79
 Flip-Flops                                            : 79
# Comparators                                          : 4
 4-bit comparator greatequal                           : 1
 4-bit comparator less                                 : 3
# Xors                                                 : 1
 1-bit xor2                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <char1_7> (without init value) has a constant value of 0 in block <ps2_test>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <char2_7> (without init value) has a constant value of 0 in block <ps2_test>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <char1_4> in Unit <ps2_test> is equivalent to the following FF/Latch, which will be removed : <char1_5> 
INFO:Xst:2261 - The FF/Latch <char2_4> in Unit <ps2_test> is equivalent to the following FF/Latch, which will be removed : <char2_5> 

Optimizing unit <ps2_test> ...

Optimizing unit <PS2_Ctrl> ...

Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <SF_D_4> in Unit <ps2_test> is equivalent to the following FF/Latch, which will be removed : <SF_D_5> 
Found area constraint ratio of 100 (+ 5) on block ps2_test, actual ratio is 1.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 84
 Flip-Flops                                            : 84

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ps2_test.ngr
Top Level Output File Name         : ps2_test
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 23

Cell Usage :
# BELS                             : 108
#      GND                         : 1
#      INV                         : 10
#      LUT2                        : 15
#      LUT2_L                      : 3
#      LUT3                        : 21
#      LUT3_L                      : 3
#      LUT4                        : 45
#      LUT4_D                      : 5
#      LUT4_L                      : 4
#      VCC                         : 1
# FlipFlops/Latches                : 84
#      FD                          : 15
#      FDC                         : 11
#      FDCE                        : 25
#      FDE                         : 28
#      FDR                         : 2
#      FDS                         : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 22
#      IBUF                        : 2
#      OBUF                        : 20
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                       68  out of   3584     1%  
 Number of Slice Flip Flops:             84  out of   7168     1%  
 Number of 4 input LUTs:                106  out of   7168     1%  
 Number of IOs:                          23
 Number of bonded IOBs:                  23  out of    141    16%  
 Number of GCLKs:                         1  out of      8    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 84    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
Reset(Reset:Q)                     | NONE(u1/Bit_Cnt_0)     | 36    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.198ns (Maximum Frequency: 138.927MHz)
   Minimum input arrival time before clock: 1.825ns
   Maximum output required time after clock: 7.271ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 7.198ns (frequency: 138.927MHz)
  Total number of paths / destination ports: 883 / 140
-------------------------------------------------------------------------
Delay:               7.198ns (Levels of Logic = 3)
  Source:            u1/Bit_Cnt_2 (FF)
  Destination:       u1/Scan_DAVi (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: u1/Bit_Cnt_2 to u1/Scan_DAVi
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             4   0.720   1.256  u1/Bit_Cnt_2 (u1/Bit_Cnt_2)
     LUT3:I0->O            1   0.551   0.827  u1/Scan_Code_not0001_SW0 (N2)
     LUT4:I3->O           11   0.551   1.339  u1/Scan_Code_not0001 (u1/Scan_Code_not0001)
     LUT2:I1->O            1   0.551   0.801  u1/Scan_DAVi_not00011 (u1/Scan_DAVi_not0001)
     FDCE:CE                   0.602          u1/Scan_DAVi
    ----------------------------------------
    Total                      7.198ns (2.975ns logic, 4.223ns route)
                                       (41.3% logic, 58.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              1.825ns (Levels of Logic = 1)
  Source:            KeyboardClock (PAD)
  Destination:       u1/Filter_7 (FF)
  Destination Clock: clk rising

  Data Path: KeyboardClock to u1/Filter_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.821   0.801  KeyboardClock_IBUF (KeyboardClock_IBUF)
     FDC:D                     0.203          u1/Filter_7
    ----------------------------------------
    Total                      1.825ns (1.024ns logic, 0.801ns route)
                                       (56.1% logic, 43.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 18 / 18
-------------------------------------------------------------------------
Offset:              7.271ns (Levels of Logic = 1)
  Source:            SF_D_7 (FF)
  Destination:       SF_D<7> (PAD)
  Source Clock:      clk rising

  Data Path: SF_D_7 to SF_D<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              3   0.720   0.907  SF_D_7 (SF_D_7)
     OBUF:I->O                 5.644          SF_D_7_OBUF (SF_D<7>)
    ----------------------------------------
    Total                      7.271ns (6.364ns logic, 0.907ns route)
                                       (87.5% logic, 12.5% route)

=========================================================================


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.19 secs
 
--> 

Total memory usage is 251668 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    5 (   0 filtered)

