library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity usart is
port(
  
                 clk 					: 	in  	std_logic;
				serial_in 			: 	in  	std_logic;
				serial_out 			: 	out  	std_logic:='1'
				
  
  );
end usart;

architecture Behavioral of usart is
      
		
		
		component SERIAL_PACK 
                generic(	oscillator_clk		:	integer		:=40000000;--7372800;--
				               baud_rate			:	integer		:=9600;
				               parity_enable		:	std_logic	:='1';
				                parity_type		:	std_logic	:='0'	-- Even='0' , Odd='1'
				                                 );
                 port ( 	
				                clk 					: 	in  	std_logic;
				                serial_in 			: 	in  	std_logic;
				                serial_out 			: 	out  	std_logic;
				                received_data		:	out	std_logic_vector(7 downto 0):=(others=>'0');
			                   send_data			:	in		std_logic_vector(7 downto 0);
				                receive_enable		:	in		std_logic;
				                send_enable			:	in		std_logic;
				                receive_flag		:	out	std_logic:='0';
			                   send_flag			:	inout std_logic:='0';
			                   receive_error		:	out	std_logic:='0'
				); 	
	      		
end component;	
---------------------------------------------------------
COMPONENT datarom
  PORT (
    clka : IN STD_LOGIC;
    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
END COMPONENT;
--------------------------------------------------- 
component icon
  PORT (
    CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));

end component;
--------
component ila
  PORT (
    CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
    CLK : IN STD_LOGIC;
    TRIG0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0));

end component;
---------------------------------- 
   signal read_data:	std_logic_vector(7 downto 0);
	signal send_data	:	std_logic_vector(7 downto 0);
	signal receive_en	:	std_logic;
	signal send_en	:	std_logic;
	signal receive_flage	:	std_logic;
	signal send_flage	:	std_logic;

	signal addra	:	std_logic_vector(7 downto 0);
	signal douta	:	std_logic_vector(7 downto 0); 
     signal wea	:	std_logic_vector(0 downto 0); 
    signal  dina 	:	std_logic_vector(7 downto 0); 
    signal  signal_test	:	std_logic_vector(7 downto 0):=x"00"; 
    signal  CONTROL	:	std_logic_vector(35 downto 0); 
    signal  TRIG0	:	std_logic_vector(63 downto 0);
	
  
 begin
----------------------------------
u1 : datarom
  PORT MAP (
    clka => clk,
    wea => wea,
    addra => addra,
    dina => dina,
    douta => douta
  );
-----------------------------------
txrx: SERIAL_PACK  
	generic map(oscillator_clk		=>50000000,
				baud_rate			=>9600,
				parity_enable		=>'0',
				parity_type			=>'0'	
				) 
    port map( 	
				clk 		=>clk,			
				serial_in =>serial_in,	 	
				serial_out =>serial_out,			
				received_data =>	read_data,	
				send_data	=>send_data,			
				receive_enable	=>receive_en,	
				send_enable	=>send_en,			
				receive_flag	=>receive_flage,		
				send_flag	=>send_flage,			
				receive_error		=> open--:	
				);

------------------------------------

chip_ila : ila
  port map (
    CONTROL => CONTROL,
    CLK => CLK,
    TRIG0 => TRIG0);

---------------------------------
chip_icon : icon
  port map (
    CONTROL0 => CONTROL);

 
--------------------------------------------------------	---		
	
	
				
				
				
				
				

---------------------------------------------------------
process(clk)

variable state    : integer range 0 to 11:=0;
variable counter : integer range 0 to 256  ;
variable cnt   : integer range 0 to 256:=0;
variable cntt   : integer range 0 to 40000000:=0;
begin
if rising_edge(clk)  then






case state is
when 0=>
receive_en<='0';
send_en<='0';
wea<=(others=>'0');
addra<=x"01";
send_data<=x"00";
state:=1;

when 1=>
receive_en<='1';
send_en<='0';
state:=2;


when 2=>
if receive_flage='1' then
state:=3;
else
state:=2;
end if;

when 3=>

     if receive_flage='0' and read_data=x"01" then
     dina<=read_data;
     wea<=(others=>'1');
     TRIG0(7 downto 0)<=read_data;

     TRIG0(8)<='1';
      state:=4;
     else
     state:=3;
     end if;




when 4=>

if receive_flage='1' then
state:=5;
else
state:=4;
end if;





when 5=>

if receive_flage='0' and read_data=x"02" then
     addra<=x"02";
     dina<=read_data;
     wea<=(others=>'1');
     TRIG0(7 downto 0)<=read_data;

     TRIG0(8)<='1';
      state:=4;
     else
     state:=3;
     end if;








if addra=10 then
addra<=x"01";
receive_en<='0';
send_data<=x"00";

state:=6;
else
addra<=addra+1;
state:=2;
end if;

when 6=>

receive_en<='0';
state:=7;
when 7=>
wea<=(others=>'0');
send_data<=douta ;
state:=8;


when 8=>


state:=9;

when 9=>
send_en<='1';
if send_flage='1'  then
state:=10;

else
state:=9;
end if;


when 10=>

if send_flage='0'  then
state:=11;
send_en<='0';
else
state:=10;
end if;


when 11=>

if addra=10 then
addra<=x"01";
state:=0;
else
addra<=addra+1;
state:=7;
end if;







end case;
end if;
end process;
end Behavioral;

