### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.

Software Version and Target Device
Product Version: | ISE:13.2 (WebPack) - O.61xd | Target Family: | Spartan3
OS Platform: | NT64 | Target Device: | xc3s400
Project ID (random number) | 8e70cb1fb2c84c808800046dc397839e.9605B31FA3594D33B6B41949340ED823.4 | Target Package: | pq208
Registration ID | __0_0_0 | Target Speed: | -4
Date Generated | 2013-12-26T23:51:17 | Tool Flow | ISE

User Environment
OS Name | Microsoft Windows 7 , 64-bit | OS Release | Service Pack 1 (build 7601)
CPU Name | Intel(R) Core(TM) i5-2450M CPU @ 2.50GHz | CPU Speed | 2494 MHz

Device Usage Statistics
Macro Statistics | Miscellaneous Statistics | Net Statistics | Site Usage
| MiscellaneousStatistics

- AGG_BONDED_IO=18
- AGG_IO=18
- AGG_SLICE=459
- NUM_4_INPUT_LUT=492
- NUM_BONDED_IOB=18
- NUM_BSCAN=1
- NUM_BUFGMUX=3
- NUM_CARRY_SKIP=3
- NUM_CYMUX=204
- NUM_DCM=1
- NUM_LUT_RT=73
- NUM_MULT18X18=1
- NUM_MULTAND=64
- NUM_RAMB16=4
- NUM_RPM=13
- NUM_SHIFT=163
- NUM_SLICEL=364
- NUM_SLICEM=95
- NUM_SLICE_FF=529
- NUM_SLICE_LATCH=1
- NUM_XOR=130
- Xilinx Core chipscope_icon_v1_04_a, Xilinx CORE Generator 13.2=1
- Xilinx Core chipscope_ila_v1_03_a, Xilinx CORE Generator 13.2=1
- Xilinx Core fir_compiler_v5_0, Xilinx CORE Generator 13.2=1

NetStatistics

- NumNets_Active=940
- NumNets_Gnd=1
- NumNets_Vcc=1
- NumNodesOfType_Active_BRAMADDR=64
- NumNodesOfType_Active_BRAMDUMMY=85
- NumNodesOfType_Active_CLKPIN=386
- NumNodesOfType_Active_CNTRLPIN=367
- NumNodesOfType_Active_DOUBLE=2063
- NumNodesOfType_Active_DUMMY=1256
- NumNodesOfType_Active_DUMMYBANK=2
- NumNodesOfType_Active_DUMMYESC=10
- NumNodesOfType_Active_GLOBAL=132
- NumNodesOfType_Active_HFULLHEX=19
- NumNodesOfType_Active_HLONG=6
- NumNodesOfType_Active_HUNIHEX=115
- NumNodesOfType_Active_INPUT=1897
- NumNodesOfType_Active_IOBOUTPUT=10
- NumNodesOfType_Active_OMUX=985
- NumNodesOfType_Active_OUTPUT=912
- NumNodesOfType_Active_PREBXBY=417
- NumNodesOfType_Active_VFULLHEX=45
- NumNodesOfType_Active_VLONG=7
- NumNodesOfType_Active_VUNIHEX=60
- NumNodesOfType_Vcc_BRAMADDR=1
- NumNodesOfType_Vcc_CNTRLPIN=38
- NumNodesOfType_Vcc_DUMMY=207
- NumNodesOfType_Vcc_INPUT=225
- NumNodesOfType_Vcc_PREBXBY=17
- NumNodesOfType_Vcc_VCCOUT=60

SiteStatistics

- IOB-DIFFM=7
- IOB-DIFFS=7
- SLICEL-SLICEM=153

SiteSummary

- BSCAN=1
- BSCAN_BSCAN_BLACKBOX=1
- BUFGMUX=3
- BUFGMUX_GCLKMUX=3
- BUFGMUX_GCLK_BUFFER=3
- DCM=1
- DCM_DCM=1
- IOB=18
- IOB_INBUF=10
- IOB_ISELMUX=1
- IOB_OUTBUF=9
- IOB_PAD=18
- IOB_TSMUX_GND=1
- MULT18X18=1
- MULT18X18_BLACKBOX=1
- RAMB16=4
- RAMB16_RAMB16=4
- RAMB16_RAMB16A=4
- RAMB16_RAMB16B=3
- SLICEL=364
- SLICEL_C1VDD=3
- SLICEL_C2VDD=1
- SLICEL_CYMUXF=69
- SLICEL_CYMUXG=59
- SLICEL_F=162
- SLICEL_F5MUX=11
- SLICEL_F6MUX=3
- SLICEL_FFX=211
- SLICEL_FFY=266
- SLICEL_G=160
- SLICEL_GNDF=40
- SLICEL_GNDG=37
- SLICEL_VDDG=1
- SLICEL_XORF=66
- SLICEL_XORG=59
- SLICEM=95
- SLICEM_CYMUXF=38
- SLICEM_CYMUXG=38
- SLICEM_F=80
- SLICEM_F5MUX=17
- SLICEM_F6MUX=6
- SLICEM_FAND=32
- SLICEM_FFX=24
- SLICEM_FFY=29
- SLICEM_FMC15_BLACKBOX=54
- SLICEM_G=90
- SLICEM_GAND=32
- SLICEM_GMC15_BLACKBOX=58
- SLICEM_GNDF=6
- SLICEM_GNDG=3
- SLICEM_VDDG=3
- SLICEM_WSGEN=89
- SLICEM_XORF=5
- SLICEM_YBUSED=3

Configuration Data
BUFGMUX

- S=[S_INV:3] [S:0]

BUFGMUX_GCLKMUX

- DISABLE_ATTR=[LOW:3]
- S=[S_INV:3] [S:0]

DCM

- PSCLK=[PSCLK_INV:0] [PSCLK:1]
- PSEN=[PSEN_INV:0] [PSEN:1]
- PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
- RST=[RST:1] [RST_INV:0]

DCM_DCM

- CLKDV_DIVIDE=[2:1]
- CLKOUT_PHASE_SHIFT=[NONE:1]
- CLK_FEEDBACK=[1X:1]
- DESKEW_ADJUST=[7:1]
- DFS_FREQUENCY_MODE=[LOW:1]
- DLL_FREQUENCY_MODE=[LOW:1]
- DUTY_CYCLE_CORRECTION=[TRUE:1]
- FACTORY_JF1=[0X80:1]
- FACTORY_JF2=[0X80:1]
- PSCLK=[PSCLK_INV:0] [PSCLK:1]
- PSEN=[PSEN_INV:0] [PSEN:1]
- PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
- RST=[RST:1] [RST_INV:0]

IOB

- O1=[O1_INV:0] [O1:9]

IOB_ISELMUX

- 0=[0:1] [0_INV:0]
- S0=[S0:1] [S0_INV:0]

IOB_OUTBUF

- IN=[IN_INV:0] [IN:9]

IOB_PAD

- DRIVEATTRBOX=[12:9]
- IOATTRBOX=[LVCMOS25:18]
- SLEW=[SLOW:9]

MULT18X18

- CE=[CE:1] [CE_INV:0]
- CLK=[CLK:1] [CLK_INV:0]
- RST=[RST:1] [RST_INV:0]

MULT18X18_BLACKBOX

- CE=[CE:1] [CE_INV:0]
- CLK=[CLK:1] [CLK_INV:0]
- RST=[RST:1] [RST_INV:0]

RAMB16

- CLKA=[CLKA_INV:0] [CLKA:4]
- CLKB=[CLKB_INV:0] [CLKB:3]
- ENA=[ENA_INV:0] [ENA:4]
- ENB=[ENB_INV:0] [ENB:3]
- SSRA=[SSRA_INV:0] [SSRA:4]
- SSRB=[SSRB_INV:0] [SSRB:3]
- WEA=[WEA:4] [WEA_INV:0]
- WEB=[WEB:3] [WEB_INV:0]

RAMB16_RAMB16A

- CLKA=[CLKA_INV:0] [CLKA:4]
- ENA=[ENA_INV:0] [ENA:4]
- PORTA_ATTR=[16384X1:2] [2048X9:2]
- SSRA=[SSRA_INV:0] [SSRA:4]
- WEA=[WEA:4] [WEA_INV:0]
- WRITEMODEA=[WRITE_FIRST:4]

RAMB16_RAMB16B

- CLKB=[CLKB_INV:0] [CLKB:3]
- ENB=[ENB_INV:0] [ENB:3]
- PORTB_ATTR=[512X36:2] [2048X9:1]
- SSRB=[SSRB_INV:0] [SSRB:3]
- WEB=[WEB:3] [WEB_INV:0]
- WRITEMODEB=[WRITE_FIRST:3]

SLICEL

- BX=[BX_INV:0] [BX:162]
- BY=[BY:192] [BY_INV:2]
- CE=[CE:67] [CE_INV:0]
- CIN=[CIN_INV:0] [CIN:59]
- CLK=[CLK:280] [CLK_INV:1]
- SR=[SR:142] [SR_INV:19]

SLICEL_CYMUXF

- 0=[0:69] [0_INV:0]
- 1=[1_INV:0] [1:69]

SLICEL_CYMUXG

- 0=[0:58] [0_INV:0]

SLICEL_F5MUX

- S0=[S0:11] [S0_INV:0]

SLICEL_F6MUX

- S0=[S0:3] [S0_INV:0]

SLICEL_FFX

- CE=[CE:44] [CE_INV:0]
- CK=[CK:211] [CK_INV:0]
- D=[D:211] [D_INV:0]
- FFX_INIT_ATTR=[INIT0:127] [INIT1:84]
- FFX_SR_ATTR=[SRLOW:143] [SRHIGH:68]
- LATCH_OR_FF=[FF:211]
- REV=[REV_INV:0] [REV:4]
- SR=[SR:111] [SR_INV:16]
- SYNC_ATTR=[ASYNC:104] [SYNC:107]

SLICEL_FFY

- CE=[CE:65] [CE_INV:0]
- CK=[CK:265] [CK_INV:1]
- D=[D:264] [D_INV:2]
- FFY_INIT_ATTR=[INIT0:176] [INIT1:90]
- FFY_SR_ATTR=[SRLOW:195] [SRHIGH:71]
- LATCH_OR_FF=[FF:265] [LATCH:1]
- SR=[SR:134] [SR_INV:19]
- SYNC_ATTR=[ASYNC:134] [SYNC:132]

SLICEL_XORF

- 1=[1_INV:0] [1:66]

SLICEM

- BX=[BX_INV:0] [BX:41]
- BY=[BY:69] [BY_INV:0]
- CE=[CE:3] [CE_INV:0]
- CIN=[CIN_INV:0] [CIN:38]
- CLK=[CLK:95] [CLK_INV:0]
- SHIFTIN=[SHIFTIN_INV:0] [SHIFTIN:26]
- SR=[SR:94] [SR_INV:0]

SLICEM_CYMUXF

- 0=[0:38] [0_INV:0]
- 1=[1_INV:0] [1:38]

SLICEM_CYMUXG

- 0=[0:35] [0_INV:0]

SLICEM_F

- DI=[DI:74] [DI_INV:0]
- F_ATTR=[SHIFT_REG:74]
- LUT_OR_MEM=[LUT:6] [RAM:74]

SLICEM_F5MUX

- S0=[S0:17] [S0_INV:0]

SLICEM_F6MUX

- S0=[S0:6] [S0_INV:0]

SLICEM_FFX

- CE=[CE:3] [CE_INV:0]
- CK=[CK:24] [CK_INV:0]
- D=[D:24] [D_INV:0]
- FFX_INIT_ATTR=[INIT0:22] [INIT1:2]
- FFX_SR_ATTR=[SRLOW:22] [SRHIGH:2]
- LATCH_OR_FF=[FF:24]
- SR=[SR:5] [SR_INV:0]
- SYNC_ATTR=[ASYNC:19] [SYNC:5]

SLICEM_FFY

- CK=[CK:29] [CK_INV:0]
- D=[D:29] [D_INV:0]
- FFY_INIT_ATTR=[INIT0:29]
- FFY_SR_ATTR=[SRLOW:29]
- LATCH_OR_FF=[FF:29]
- SYNC_ATTR=[ASYNC:28] [SYNC:1]

SLICEM_G

- DI=[DI:89] [DI_INV:0]
- G_ATTR=[SHIFT_REG:89]
- LUT_OR_MEM=[LUT:1] [RAM:89]

SLICEM_WSGEN

- CK=[CK:89] [CK_INV:0]
- SYNC_ATTR=[ASYNC:28]
- WE=[WE_INV:0] [WE:89]

SLICEM_XORF

- 1=[1_INV:0] [1:5]

Pin Data
BSCAN

- DRCK1=1
- SEL1=1
- SHIFT=1
- TDI=1
- TDO1=1
- TDO2=1
- UPDATE=1

BSCAN_BSCAN_BLACKBOX

- DRCK1=1
- SEL1=1
- SHIFT=1
- TDI=1
- TDO1=1
- TDO2=1
- UPDATE=1

BUFGMUX

- I0=3
- O=3
- S=3

BUFGMUX_GCLKMUX

- I0=3
- OUT=3
- S=3

BUFGMUX_GCLK_BUFFER

- IN=3
- OUT=3

DCM

- CLK0=1
- CLKDV=1
- CLKFB=1
- CLKIN=1
- PSCLK=1
- PSEN=1
- PSINCDEC=1
- RST=1

DCM_DCM

- CLK0=1
- CLKDV=1
- CLKFB=1
- CLKIN=1
- PSCLK=1
- PSEN=1
- PSINCDEC=1
- RST=1

IOB

- I=10
- O1=9
- PAD=18

IOB_INBUF

- IN=10
- OUT=10

IOB_ISELMUX

- 0=1
- 1=1
- OUT=1
- S0=1

IOB_OUTBUF

- IN=9
- OUT=9

IOB_PAD

- PAD=18

IOB_TSMUX_GND

- 0=1

MULT18X18

- A0=1
- A1=1
- A10=1
- A11=1
- A12=1
- A13=1
- A14=1
- A15=1
- A16=1
- A17=1
- A2=1
- A3=1
- A4=1
- A5=1
- A6=1
- A7=1
- A8=1
- A9=1
- B0=1
- B1=1
- B10=1
- B11=1
- B12=1
- B13=1
- B14=1
- B15=1
- B16=1
- B17=1
- B2=1
- B3=1
- B4=1
- B5=1
- B6=1
- B7=1
- B8=1
- B9=1
- CE=1
- CLK=1
- P0=1
- P1=1
- P10=1
- P11=1
- P12=1
- P13=1
- P14=1
- P15=1
- P16=1
- P2=1
- P3=1
- P4=1
- P5=1
- P6=1
- P7=1
- P8=1
- P9=1
- RST=1

MULT18X18_BLACKBOX

- A0=1
- A1=1
- A10=1
- A11=1
- A12=1
- A13=1
- A14=1
- A15=1
- A16=1
- A17=1
- A2=1
- A3=1
- A4=1
- A5=1
- A6=1
- A7=1
- A8=1
- A9=1
- B0=1
- B1=1
- B10=1
- B11=1
- B12=1
- B13=1
- B14=1
- B15=1
- B16=1
- B17=1
- B2=1
- B3=1
- B4=1
- B5=1
- B6=1
- B7=1
- B8=1
- B9=1
- CE=1
- CLK=1
- P0=1
- P1=1
- P10=1
- P11=1
- P12=1
- P13=1
- P14=1
- P15=1
- P16=1
- P2=1
- P3=1
- P4=1
- P5=1
- P6=1
- P7=1
- P8=1
- P9=1
- RST=1

RAMB16

- ADDRA0=2
- ADDRA1=2
- ADDRA10=4
- ADDRA11=4
- ADDRA12=4
- ADDRA13=4
- ADDRA2=2
- ADDRA3=4
- ADDRA4=4
- ADDRA5=4
- ADDRA6=4
- ADDRA7=4
- ADDRA8=4
- ADDRA9=4
- ADDRB10=3
- ADDRB11=3
- ADDRB12=3
- ADDRB13=3
- ADDRB3=1
- ADDRB4=1
- ADDRB5=3
- ADDRB6=3
- ADDRB7=3
- ADDRB8=3
- ADDRB9=3
- CLKA=4
- CLKB=3
- DIA0=3
- DIA1=1
- DIA2=1
- DIA3=1
- DIA4=1
- DIA5=1
- DIA6=1
- DIA7=1
- DIB0=3
- DIB1=3
- DIB10=2
- DIB11=2
- DIB12=2
- DIB13=2
- DIB14=2
- DIB15=2
- DIB16=2
- DIB17=2
- DIB18=2
- DIB19=2
- DIB2=3
- DIB20=2
- DIB21=2
- DIB22=2
- DIB23=2
- DIB24=2
- DIB25=2
- DIB26=2
- DIB27=2
- DIB28=2
- DIB29=2
- DIB3=3
- DIB30=2
- DIB31=2
- DIB4=3
- DIB5=3
- DIB6=3
- DIB7=3
- DIB8=2
- DIB9=2
- DIPA0=1
- DIPB0=3
- DIPB1=2
- DIPB2=2
- DIPB3=2
- DOA0=4
- DOA1=2
- DOA2=2
- DOA3=2
- DOA4=2
- DOA5=2
- DOA6=2
- DOA7=2
- DOB0=1
- DOB1=1
- DOB2=1
- DOB3=1
- DOB4=1
- DOB5=1
- DOB6=1
- DOB7=1
- ENA=4
- ENB=3
- SSRA=4
- SSRB=3
- WEA=4
- WEB=3

RAMB16_RAMB16

- ADDRA=4
- ADDRB=3
- DIA=4
- DIB=3
- DOA=4
- DOB=3

RAMB16_RAMB16A

- ADDRA=4
- ADDRA0=2
- ADDRA1=2
- ADDRA10=4
- ADDRA11=4
- ADDRA12=4
- ADDRA13=4
- ADDRA2=2
- ADDRA3=4
- ADDRA4=4
- ADDRA5=4
- ADDRA6=4
- ADDRA7=4
- ADDRA8=4
- ADDRA9=4
- CLKA=4
- DIA=4
- DIA0=3
- DIA1=1
- DIA2=1
- DIA3=1
- DIA4=1
- DIA5=1
- DIA6=1
- DIA7=1
- DIPA0=1
- DOA=4
- DOA0=4
- DOA1=2
- DOA2=2
- DOA3=2
- DOA4=2
- DOA5=2
- DOA6=2
- DOA7=2
- ENA=4
- SSRA=4
- WEA=4

RAMB16_RAMB16B

- ADDRB=3
- ADDRB10=3
- ADDRB11=3
- ADDRB12=3
- ADDRB13=3
- ADDRB3=1
- ADDRB4=1
- ADDRB5=3
- ADDRB6=3
- ADDRB7=3
- ADDRB8=3
- ADDRB9=3
- CLKB=3
- DIB=3
- DIB0=3
- DIB1=3
- DIB10=2
- DIB11=2
- DIB12=2
- DIB13=2
- DIB14=2
- DIB15=2
- DIB16=2
- DIB17=2
- DIB18=2
- DIB19=2
- DIB2=3
- DIB20=2
- DIB21=2
- DIB22=2
- DIB23=2
- DIB24=2
- DIB25=2
- DIB26=2
- DIB27=2
- DIB28=2
- DIB29=2
- DIB3=3
- DIB30=2
- DIB31=2
- DIB4=3
- DIB5=3
- DIB6=3
- DIB7=3
- DIB8=2
- DIB9=2
- DIPB0=3
- DIPB1=2
- DIPB2=2
- DIPB3=2
- DOB=3
- DOB0=1
- DOB1=1
- DOB2=1
- DOB3=1
- DOB4=1
- DOB5=1
- DOB6=1
- DOB7=1
- ENB=3
- SSRB=3
- WEB=3

SLICEL

- BX=162
- BY=194
- CE=67
- CIN=59
- CLK=281
- COUT=59
- F1=158
- F2=121
- F3=91
- F4=60
- F5=6
- FXINA=3
- FXINB=3
- G1=159
- G2=122
- G3=96
- G4=63
- SR=161
- X=69
- XB=2
- XQ=211
- Y=68
- YQ=266

SLICEL_C1VDD

- 1=3

SLICEL_C2VDD

- 1=1

SLICEL_CYMUXF

- 0=69
- 1=69
- OUT=69
- S0=69

SLICEL_CYMUXG

- 0=58
- 1=59
- OUT=59
- S0=59

SLICEL_F

- A1=158
- A2=121
- A3=91
- A4=60
- D=162

SLICEL_F5MUX

- F=11
- G=11
- OUT=11
- S0=11

SLICEL_F6MUX

- 0=3
- 1=3
- OUT=3
- S0=3

SLICEL_FFX

- CE=44
- CK=211
- D=211
- Q=211
- REV=4
- SR=127

SLICEL_FFY

- CE=65
- CK=266
- D=266
- Q=266
- SR=153

SLICEL_G

- A1=159
- A2=122
- A3=96
- A4=63
- D=160

SLICEL_GNDF

- 0=40

SLICEL_GNDG

- 0=37

SLICEL_VDDG

- 1=1

SLICEL_XORF

- 0=66
- 1=66
- O=66

SLICEL_XORG

- 0=59
- 1=59
- O=59

SLICEM

- BX=41
- BY=69
- CE=3
- CIN=38
- CLK=95
- COUT=38
- F1=75
- F2=75
- F3=74
- F4=74
- F5=12
- FXINA=6
- FXINB=6
- G1=90
- G2=90
- G3=90
- G4=89
- SHIFTIN=26
- SHIFTOUT=26
- SR=94
- X=6
- XB=28
- XQ=24
- Y=12
- YB=3
- YQ=29

SLICEM_CYMUXF

- 0=38
- 1=38
- OUT=38
- S0=38

SLICEM_CYMUXG

- 0=35
- 1=38
- OUT=38
- S0=38

SLICEM_F

- A1=75
- A2=75
- A3=74
- A4=74
- D=80
- DI=74
- WS=74

SLICEM_F5MUX

- F=17
- G=17
- OUT=17
- S0=17

SLICEM_F6MUX

- 0=6
- 1=6
- OUT=6
- S0=6

SLICEM_FAND

- 0=32
- 1=32
- O=32

SLICEM_FFX

- CE=3
- CK=24
- D=24
- Q=24
- SR=5

SLICEM_FFY

- CK=29
- D=29
- Q=29

SLICEM_FMC15_BLACKBOX

- MC15=54
- WS2=54

SLICEM_G

- A1=90
- A2=90
- A3=90
- A4=89
- D=87
- DI=89
- WS=89

SLICEM_GAND

- 0=32
- 1=32
- O=32

SLICEM_GMC15_BLACKBOX

- MC15=58
- WS2=58

SLICEM_GNDF

- 0=6

SLICEM_GNDG

- 0=3

SLICEM_VDDG

- 1=3

SLICEM_WSGEN

- CK=89
- WE=89
- WSF=74
- WSG=89

SLICEM_XORF

- 0=5
- 1=5
- O=5

SLICEM_YBUSED

- 0=3
- OUT=3

Tool Usage
Command Line History

- xst -intstyle ise -ifn <ise_file>
- xst -intstyle ise -ifn <ise_file>
- xst -intstyle ise -ifn <ise_file>
- ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-4 <ise_file> <fname>.ngd
- xst -intstyle ise -ifn <ise_file>
- ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-4 <ise_file> <fname>.ngd
- map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
- par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
- trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
- bitgen -intstyle ise -f <fname>.ut <fname>.ncd
- xst -intstyle ise -ifn <ise_file>
- ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-4 <ise_file> <fname>.ngd
- map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
- par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
- bitgen -intstyle ise -f <fname>.ut <fname>.ncd
- xst -intstyle ise -ifn <ise_file>
- ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-4 <ise_file> <fname>.ngd
- map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
- par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
- trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
- bitgen -intstyle ise -f <fname>.ut <fname>.ncd
- xst -intstyle ise -ifn <ise_file>
- xst -intstyle ise -ifn <ise_file>
- xst -intstyle ise -ifn <ise_file>
- ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-4 <ise_file> <fname>.ngd
- map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
- par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
- trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
- bitgen -intstyle ise -f <fname>.ut <fname>.ncd

Software Quality
Run Statistics
Program Name | Runs Started | Runs Finished | Errors | Fatal Errors | Internal Errors | Exceptions | Core Dumps
_impact | 18 | 8 | 0 | 0 | 0 | 0 | 0
arwz | 7 | 7 | 0 | 0 | 0 | 0 | 0
bitgen | 185 | 185 | 0 | 0 | 0 | 0 | 0
cse_server | 7 | 6 | 0 | 0 | 0 | 0 | 0
edif2ngd | 2 | 2 | 0 | 0 | 0 | 0 | 0
map | 192 | 190 | 0 | 0 | 0 | 0 | 0
ngcbuild | 13 | 13 | 0 | 0 | 0 | 0 | 0
ngdbuild | 198 | 197 | 0 | 0 | 0 | 0 | 0
obngc | 2 | 2 | 0 | 0 | 0 | 0 | 0
par | 190 | 185 | 4 | 0 | 0 | 0 | 0
partgen | 29 | 27 | 0 | 0 | 0 | 0 | 0
trce | 181 | 181 | 0 | 0 | 0 | 0 | 0
xst | 307 | 307 | 0 | 0 | 0 | 0 | 0

Project Statistics
PROP_Enable_Message_Filtering=false | PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced | PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false | PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) | PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL | PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor | PROP_intProjectCreationTimestamp=2013-12-22T01:49:56
PROP_intWbtProjectID=9605B31FA3594D33B6B41949340ED823 | PROP_intWbtProjectIteration=4
PROP_intWorkingDirLocWRTProjDir=Same | PROP_intWorkingDirUsed=No
PROP_AutoTop=true | PROP_DevFamily=Spartan3
PROP_DevDevice=xc3s400 | PROP_DevFamilyPMName=spartan3
PROP_DevPackage=pq208 | PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 | PROP_PreferredLanguage=VHDL
FILE_COREGEN=2 | FILE_SYSGENISE=1
FILE_UCF=1 | FILE_VHDL=4
FILE_XAW=1

Core Statistics
Core Type=fir_compiler_v5_0
accum_width=23 | allow_approx=0 | c_has_ce=1 | c_has_data_valid=0
c_has_nd=1 | c_has_sclr=0 | c_latency=53 | c_mem_init_file=fname.mif
c_optimization=1 | chan_in_adv=0 | chan_sel_width=1 | clock_freq=450
coef_memtype=0 | coef_reload=0 | coef_type=0 | coef_width=8
col_config=1 | col_mode=0 | col_pipe_len=4 | data_memtype=0
data_type=0 | data_width=8 | datapath_memtype=0 | decim_rate=1
filter_arch=1 | filter_sel_width=1 | filter_type=0 | interp_rate=1
ipbuff_memtype=0 | neg_symmetry=0 | num_channels=1 | num_filts=1
num_paths=1 | num_taps=92 | odd_symmetry=0 | opbuff_memtype=0
output_reg=1 | output_width=8 | rate_change_type=0 | round_mode=6
sample_freq=1 | sclr_deterministic=0 | symmetry=1 | zero_packing_factor=1
Core Type=chipscope_icon_v1_04_a
c_build_revision=0 | c_core_major_ver=1 | c_core_minor_alpha_ver=97 | c_core_minor_ver=4
c_core_type=1 | c_major_version=13 | c_mfg_id=1 | c_minor_version=2
c_num_control_ports=1 | c_part_idcode_register=0 | c_use_bufr=0 | c_use_control0=1
c_use_control1=0 | c_use_control10=0 | c_use_control11=0 | c_use_control12=0
c_use_control13=0 | c_use_control14=0 | c_use_control2=0 | c_use_control3=0
c_use_control4=0 | c_use_control5=0 | c_use_control6=0 | c_use_control7=0
c_use_control8=0 | c_use_control9=0 | c_use_ext_bscan=0 | c_use_jtag_bufg=1
c_use_new_parser=1 | c_use_sim=0 | c_use_softbscan=0 | c_use_unused_bscan=0
c_use_xst_tck_workaround=1 | c_user_scan_chain=1 | c_xco_list=Number_Control_Ports=1;Use_Ext_Bscan=false;User_Scan_Chain=USER1;Enable_Jtag_Bufg=true;Use_Unused_Bscan=false;Use_Softbscan=false | c_xdevicefamily=spartan3
Core Type=chipscope_ila_v1_03_a
c_build_revision=0 | c_core_major_ver=1 | c_core_minor_alpha_ver=97 | c_core_minor_ver=3
c_core_type=2 | c_data_depth=512 | c_data_width=1 | c_ext_cap_pin_mode=0
c_ext_cap_rate_mode=0 | c_ext_cap_use_reg=1 | c_m0_tpid=0 | c_m0_type=7
c_m10_tpid=10 | c_m10_type=0 | c_m11_tpid=11 | c_m11_type=0
c_m12_tpid=12 | c_m12_type=0 | c_m13_tpid=13 | c_m13_type=0
c_m14_tpid=14 | c_m14_type=0 | c_m15_tpid=15 | c_m15_type=0
c_m1_tpid=1 | c_m1_type=0 | c_m2_tpid=2 | c_m2_type=0
c_m3_tpid=3 | c_m3_type=0 | c_m4_tpid=4 | c_m4_type=0
c_m5_tpid=5 | c_m5_type=0 | c_m6_tpid=6 | c_m6_type=0
c_m7_tpid=7 | c_m7_type=0 | c_m8_tpid=8 | c_m8_type=0
c_m9_tpid=9 | c_m9_type=0 | c_major_version=13 | c_mcnt0_width=1
c_mcnt10_width=1 | c_mcnt11_width=1 | c_mcnt12_width=1 | c_mcnt13_width=1
c_mcnt14_width=1 | c_mcnt15_width=1 | c_mcnt1_width=1 | c_mcnt2_width=1
c_mcnt3_width=1 | c_mcnt4_width=1 | c_mcnt5_width=1 | c_mcnt6_width=1
c_mcnt7_width=1 | c_mcnt8_width=1 | c_mcnt9_width=1 | c_mfg_id=1
c_minor_version=2 | c_num_ext_cap_pins=8 | c_num_match_units=1 | c_num_tseq_cnt=0
c_num_tseq_states=1 | c_ram_type=1 | c_srl16_type=2 | c_tc_mcnt_width=1
c_timestamp_depth=512 | c_timestamp_type=0 | c_timestamp_width=32 | c_trig0_width=32
c_trig10_width=1 | c_trig11_width=1 | c_trig12_width=1 | c_trig13_width=1
c_trig14_width=1 | c_trig15_width=1 | c_trig1_width=1 | c_trig2_width=1
c_trig3_width=1 | c_trig4_width=1 | c_trig5_width=1 | c_trig6_width=1
c_trig7_width=1 | c_trig8_width=1 | c_trig9_width=1 | c_tseq_cnt0_width=1
c_tseq_cnt1_width=1 | c_tseq_type=0 | c_use_atc_clkin=0 | c_use_data=0
c_use_gap=0 | c_use_inv_clk=0 | c_use_mcnt0=0 | c_use_mcnt1=0
c_use_mcnt10=0 | c_use_mcnt11=0 | c_use_mcnt12=0 | c_use_mcnt13=0
c_use_mcnt14=0 | c_use_mcnt15=0 | c_use_mcnt2=0 | c_use_mcnt3=0
c_use_mcnt4=0 | c_use_mcnt5=0 | c_use_mcnt6=0 | c_use_mcnt7=0
c_use_mcnt8=0 | c_use_mcnt9=0 | c_use_rpm=1 | c_use_storage_qual=1
c_use_tc_mcnt=0 | c_use_trig0=1 | c_use_trig1=0 | c_use_trig10=0
c_use_trig11=0 | c_use_trig12=0 | c_use_trig13=0 | c_use_trig14=0
c_use_trig15=0 | c_use_trig2=0 | c_use_trig3=0 | c_use_trig4=0
c_use_trig5=0 | c_use_trig6=0 | c_use_trig7=0 | c_use_trig8=0
c_use_trig9=0 | c_use_trig_out=0 | c_use_trigdata0=1 | c_use_trigdata1=0
c_use_trigdata10=0 | c_use_trigdata11=0 | c_use_trigdata12=0 | c_use_trigdata13=0
c_use_trigdata14=0 | c_use_trigdata15=0 | c_use_trigdata2=0 | c_use_trigdata3=0
c_use_trigdata4=0 | c_use_trigdata5=0 | c_use_trigdata6=0 | c_use_trigdata7=0
c_use_trigdata8=0 | c_use_trigdata9=0 | c_xco_list=Component_Name=ila;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=1;Use_RPMs=true;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=512;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=32;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=range_with_edges;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=8;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic_with_edges;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=8;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic_with_edges;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=8;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic_with_edges;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=8;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic_with_edges;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=8;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic_with_edges;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=8;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic_with_edges;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=8;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic_with_edges;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=8;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic_with_edges;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=8;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic_with_edges;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=8;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic_with_edges;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=8;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic_with_edges;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=8;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic_with_edges;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=8;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic_with_edges;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=8;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic_with_edges;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=8;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic_with_edges;Exclude_From_Data_Storage_16=false | c_xdevicefamily=spartan3
Core Type=sysgen_core
clock_period=10.00000000 | clocking=Clock_Enables | compilation=HDL_Netlist | sample_periods=1.00000000000 450.00000000000
testbench=1 | total_blocks=53 | xilinx_copyright_notice_block=1 | xilinx_fdatool_interface_block=1
xilinx_fir_compiler_5_0_block=1 | xilinx_gateway_in_block=1 | xilinx_gateway_out_block=1 | xilinx_register_block=2
xilinx_system_generator_block=1

Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=3 | NGDBUILD_NUM_DCM=1 | NGDBUILD_NUM_FD=33 | NGDBUILD_NUM_FDC=1
NGDBUILD_NUM_FDCE=24 | NGDBUILD_NUM_FDE=65 | NGDBUILD_NUM_FDP=33 | NGDBUILD_NUM_FDPE=129
NGDBUILD_NUM_FDR=51 | NGDBUILD_NUM_FDRE=121 | NGDBUILD_NUM_FDRS=4 | NGDBUILD_NUM_FDRSE=67
NGDBUILD_NUM_FDS=12 | NGDBUILD_NUM_FDSE=1 | NGDBUILD_NUM_GND=7 | NGDBUILD_NUM_IBUF=9
NGDBUILD_NUM_IBUFG=1 | NGDBUILD_NUM_INV=8 | NGDBUILD_NUM_LDC=1 | NGDBUILD_NUM_LUT1=74
NGDBUILD_NUM_LUT2=61 | NGDBUILD_NUM_LUT3=66 | NGDBUILD_NUM_LUT3_L=1 | NGDBUILD_NUM_LUT4=145
NGDBUILD_NUM_LUT4_L=1 | NGDBUILD_NUM_MULT18X18S=1 | NGDBUILD_NUM_MULT_AND=64 | NGDBUILD_NUM_MUXCY=29
NGDBUILD_NUM_MUXCY_D=7 | NGDBUILD_NUM_MUXCY_L=176 | NGDBUILD_NUM_MUXF5=28 | NGDBUILD_NUM_MUXF6=9
NGDBUILD_NUM_OBUF=9 | NGDBUILD_NUM_SRL16=32 | NGDBUILD_NUM_SRLC16E=131 | NGDBUILD_NUM_VCC=5
NGDBUILD_NUM_XORCY=126
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BSCAN_SPARTAN3=1 | NGDBUILD_NUM_BUFG=3 | NGDBUILD_NUM_DCM=1 | NGDBUILD_NUM_FD=33
NGDBUILD_NUM_FDC=1 | NGDBUILD_NUM_FDCE=24 | NGDBUILD_NUM_FDE=65 | NGDBUILD_NUM_FDP=33
NGDBUILD_NUM_FDPE=129 | NGDBUILD_NUM_FDR=51 | NGDBUILD_NUM_FDRE=121 | NGDBUILD_NUM_FDRS=4
NGDBUILD_NUM_FDRSE=67 | NGDBUILD_NUM_FDS=12 | NGDBUILD_NUM_FDSE=1 | NGDBUILD_NUM_GND=8
NGDBUILD_NUM_IBUF=9 | NGDBUILD_NUM_IBUFG=1 | NGDBUILD_NUM_INV=8 | NGDBUILD_NUM_LDC=1
NGDBUILD_NUM_LUT1=74 | NGDBUILD_NUM_LUT2=61 | NGDBUILD_NUM_LUT3=66 | NGDBUILD_NUM_LUT3_L=1
NGDBUILD_NUM_LUT4=145 | NGDBUILD_NUM_LUT4_L=1 | NGDBUILD_NUM_MULT18X18S=1 | NGDBUILD_NUM_MULT_AND=64
NGDBUILD_NUM_MUXCY=29 | NGDBUILD_NUM_MUXCY_D=7 | NGDBUILD_NUM_MUXCY_L=176 | NGDBUILD_NUM_MUXF5=28
NGDBUILD_NUM_MUXF6=9 | NGDBUILD_NUM_OBUF=9 | NGDBUILD_NUM_RAMB16_S1_S36=2 | NGDBUILD_NUM_RAMB16_S9=1
NGDBUILD_NUM_RAMB16_S9_S9=1 | NGDBUILD_NUM_SRLC16E=163 | NGDBUILD_NUM_TIMESPEC=1 | NGDBUILD_NUM_TS_TIMESPEC=1
NGDBUILD_NUM_VCC=6 | NGDBUILD_NUM_XORCY=126

XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj | -ifmt=mixed | -ofn=<design_top> | -ofmt=NGC
-p=xc3s400-4-pq208 | -top=<design_top> | -opt_mode=Speed | -opt_level=1
-iuc=NO | -keep_hierarchy=No | -netlist_hierarchy=As_Optimized | -rtlview=Yes
-glob_opt=AllClockNets | -read_cores=YES | -sd=<No customer specific name> | -write_timing_constraints=NO
-cross_clock_analysis=NO | -bus_delimiter=<> | -slice_utilization_ratio=100 | -bram_utilization_ratio=100
-verilog2001=YES | -fsm_extract=YES | -fsm_encoding=Auto | -safe_implementation=No
-fsm_style=LUT | -ram_extract=Yes | -ram_style=Auto | -rom_extract=Yes
-shreg_extract=YES | -rom_style=Auto | -auto_bram_packing=NO | -resource_sharing=YES
-async_to_sync=NO | -mult_style=Auto | -iobuf=YES | -max_fanout=500
-bufg=8 | -register_duplication=YES | -register_balancing=No | -optimize_primitives=NO
-use_clock_enable=Yes | -use_sync_set=Yes | -use_sync_reset=Yes | -iob=Auto
-equivalent_register_removal=YES | -slice_utilization_ratio_maxmargin=5