----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:02:37 12/23/2013 
-- Design Name: 
-- Module Name:    vga - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vga is
port(
clk:in std_logic;
reset:in std_logic;

RGB:out std_logic_vector(2 downto 0);
hsync :out std_logic;
vsync :out std_logic

);

end vga;

architecture Behavioral of vga is
 

constant           H_PIXELS      :integer range 0 to 806:=0;
constant           H_FRONTPORCH  :integer range 0 to 37:=0; 
constant           H_SYNCTIME    :integer range 0 to 128:=0; 
constant           H_BACKPORCH   :integer range 0 to 85:=0; 
constant           H_SYNCSTART   :integer range 0 to 843:=0; -- H_PIXELS + H_FRONTPORCH,
constant           H_SYNCEND     :integer range 0 to 971:=0; -- H_SYNCSTART + H_SYNCTIME,
constant           H_PERIOD      :integer range 0 to 1056:=0; --H_SYNCEND + H_BACKPORCH,
 --Vertical timing constants
constant          V_LINES       :integer range 0 to 604:=0;          
--constant          V_FRONTPORCH  :integer range 0 to -1:=0; 
constant         V_SYNCTIME    :integer range 0 to 4:=0; 
constant         V_BACKPORCH   :integer range 0 to 21:=0; 
constant         V_SYNCSTART   :integer range 0 to 603:=0;--V_LINES + V_FRONTPORCH,
constant         V_SYNCEND     :integer range 0 to 607:=0; -- V_SYNCSTART + V_SYNCTIME,
constant        V_PERIOD      :integer range 0 to 628:=0;--V_SYNCEND + V_BACKPORCH;
-------------------------
   
 signal hcnt,vcnt:std_logic_vector(10 downto 0);
 signal enable,hsyncint:std_logic;





begin
-------------------------------------
---Horizontal counter of pixels------
-------------------------------------
process(clk,reset)
begin


if reset='0' then
  hcnt <= (others=>'0');
elsif rising_edge(clk) then

if(hcnt<H_PERIOD) then
   hcnt <= hcnt + 1; 
 else
  hcnt <=(others=>'0');
end if;
end if;
end process;






--------------------------------------------------------------------------------
----Internal horizontal synchronization pulse generation (negative polarity)----
--------------------------------------------------------------------------------

process(clk,reset)
begin


if reset='0' then
  hsyncint<= '1';
elsif rising_edge(clk) then
 hsync <= hsyncint;
  
if(hcnt >= H_SYNCSTART and hcnt < H_SYNCEND) then
  hsyncint <= '0'; 
 else
  hsyncint<= '1'; 
end if;

end if;

end process;
-------------------------------------
----Vertical counter of lines--------
-------------------------------------
process(clk,reset)
begin


if reset='0' then
  vcnt<=(others=>'0');
elsif rising_edge(clk) then
  
if(vcnt < V_PERIOD) then
 vcnt <= vcnt + 1;
 else
 vcnt<=(others=>'0');
end if;

end if;

end process;
------------------------------------------------------------------------
---Vertical synchronization pulse generation (negative polarity)--------
------------------------------------------------------------------------

process(clk,reset)
begin


if reset='0' then
 vsync <='1';
elsif rising_edge(clk) then
  
if(vcnt >= V_SYNCSTART and vcnt < V_SYNCEND) then
vsync <='0';
else 
 vsync <='1';

end if;
end if;
end process;
---------------------------------------------
------Enabling of color outputs--------------
---------------------------------------------
process(clk,reset)
begin
if reset='0' then
 enable<='0';
elsif rising_edge(clk) then

if(hcnt >= H_PIXELS or vcnt >= V_LINES) then
  enable<='1';  
 else
  enable<='0'; 
end if;

end if;

end process;
---------------------------------------------------------------------------
---Output image generation (horizontal or vertical color stripes)----------
---------------------------------------------------------------------------
process(enable ,hcnt ,vcnt)
begin

if(enable ='0') then
   rgb <= "000";

else
 
if(vcnt<75) then
   rgb<="001";
elsif(vcnt<150) then
    rgb<="010";
elsif(vcnt<225) then
    rgb<="011";
elsif(vcnt<300)  then
   rgb<="100";
elsif(vcnt<375)  then
     rgb<="101";
elsif(vcnt<450) then
      rgb<="110";
elsif(vcnt<525) then
     rgb<="111";
      else
      rgb<="000";
  end if;


end if;
end process;
---------------------------
end Behavioral;



