--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:39:23 12/17/2013
-- Design Name:   
-- Module Name:   D:/tadris/fpga/eval board project/projects/spi2/tbnvhd.vhd
-- Project Name:  spi2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: spi_test
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tbnvhd IS
END tbnvhd;
 
ARCHITECTURE behavior OF tbnvhd IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT spi_test
    PORT(
         miso : IN  std_logic;
         clk : IN  std_logic;
         sclk : buffer  std_logic;
         ss_n : buffer  std_logic_vector(0 downto 0);
         mosi : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal miso : std_logic := '0';
   signal clk : std_logic := '0';

 	--Outputs
   signal sclk : std_logic;
   signal ss_n : std_logic_vector(0 downto 0);
   signal mosi : std_logic;

   -- Clock period definitions
   constant clk_period : time := 25 ns;
  -- constant sclk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: spi_test PORT MAP (
          miso => miso,
          clk => clk,
          sclk => sclk,
          ss_n => ss_n,
          mosi => mosi
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 
--   sclk_process :process
--   begin
--		sclk <= '0';
--		wait for sclk_period/2;
--		sclk <= '1';
--		wait for sclk_period/2;
--   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
     -- wait for 100 ns;	

      --wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
