----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    01:50:13 12/22/2013 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity top is
port(
adc_data:in std_logic_vector(7 downto 0);
clk:in std_logic;
dac_out:out std_logic_vector(6 downto 0);
adc_clk:buffer std_logic
);



end top;

architecture Behavioral of top is
-------------------------------
COMPONENT lab7_solution_cw 
  port (
    ce: in std_logic := '1'; 
    clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
    gateway_in: in std_logic_vector(7 downto 0); 
    fir_output: out std_logic_vector(7 downto 0)
  );
	END COMPONENT;
-----------------------------
COMPONENT clk_dcm
	PORT(
		CLKIN_IN : IN std_logic;          
		CLKDV_OUT : OUT std_logic;
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic
		);
	END COMPONENT;
	
--------------------------------------
	component ila
  PORT (
    CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
    CLK : IN STD_LOGIC;
    TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));

end component;
------------------
component icon
  PORT (
    CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));

end component;
-------------------------
signal CONTROL :  STD_LOGIC_VECTOR(35 DOWNTO 0);
signal TRIG0 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
signal CLK_10M :  STD_LOGIC;
signal CLK0_OUT :  STD_LOGIC;
signal CLKIN_IBUFG_OUT :  STD_LOGIC;
signal CLK_IN :  STD_LOGIC;
------
signal dac :  STD_LOGIC_VECTOR(7 DOWNTO 0);



begin
-------------------


adc_clk<=CLK_10M;
TRIG0(7 downto 0)<=adc_data;
--dac_out<=adc_data(6 downto 0);
dac_out<='1'&dac(6 downto 1);

----------------------
u3: lab7_solution_cw 
  port map(
    ce=> '1',
    clk=> CLK_10M  ,
    gateway_in=>adc_data   , 
    fir_output=>dac
  );
	





--I0 : IBUF 
--generic map ( CAPACITANCE => "DONT_CARE",
--              IBUF_DELAY_VALUE => "0",
--             IBUF_LOW_PWR => TRUE,
--              IFD_DELAY_VALUE => "AUTO",
--              IOSTANDARD => "DEFAULT" ) 
-- port map
-- ( O => clk_in,
--   I => CLK
-- );
 
-----------
Obuf_clk : OBUF
   generic map (
     --DRIVE => 24,
      IOSTANDARD => "DEFAULT"
     )
  port map (
     O => CLK_in ,
     I => clk
   );   



----------------
Inst_clk_dcm: clk_dcm PORT MAP(
		CLKIN_IN =>CLK_IN ,
		CLKDV_OUT =>CLK_10M ,
		CLKIN_IBUFG_OUT =>CLKIN_IBUFG_OUT ,
		CLK0_OUT =>CLK0_OUT 
	);
---------------------------
u1 : ila
  port map (
    CONTROL => CONTROL,
    CLK => CLK_10M,
    TRIG0 => TRIG0);
-------------
u2 : icon
  port map (
    CONTROL0 => CONTROL);



end Behavioral;

