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-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:48:50 12/19/2013 
-- Design Name: 
-- Module Name:    test - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test is
port( clk    : in std_logic;
        rst    : in std_logic;
        SF_D   : out std_logic_vector(7 downto 0);
        LCD_E  : out std_logic; 
        LCD_RS : out std_logic; 
        LCD_RW : out std_logic;
        SF_CE0 : out std_logic);

end test;

architecture Behavioral of test is

begin

process(clk)
variable state:integer range 0 to 15:=0;
variable cnt:integer range 0 to 5000:=0;
begin
if rising_edge(clk) then 
case state is

when 0=>

if cnt=20 then
cnt:=0;
LCD_E  <='0';
state:=1;
else
cnt:=cnt+1;
SF_D<=x"38";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=0;

end if;

when 1=>
if cnt=1600 then
state:=2;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"38";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=1;
end if;

when 2=>
if cnt=20 then
cnt:=0;
LCD_E  <='0';
state:=3;
else
SF_D<=x"0c";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=2;
cnt:=cnt+1;
end if;

when 3=>
if cnt=1600 then
state:=4;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"0c";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=3;
end if;
when 4=>

if cnt=20 then
cnt:=0;
LCD_E <='0';
state:=5;
else
SF_D<=x"01";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=4;
cnt:=cnt+1;
end if;
when 5=>
if cnt=1600 then
state:=6;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"01";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=5;
end if;

when 6=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=7;
else
SF_D<=x"06";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=6;
cnt:=cnt+1;
end if;

when 7=>
if cnt=1600 then
state:=8;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"06";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=7;
end if;

when 8=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=9;
else
SF_D<=x"80";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=8;
cnt:=cnt+1;
end if;

when 9=>
if cnt=1500 then
state:=10;
cnt:=0;
else
cnt:=cnt+1;
SF_D<=x"80";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=9;
end if;
when 10=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=11;
else
SF_D<=x"31";
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=10;
cnt:=cnt+1;
end if;

when 11=>
if cnt=1600 then
state:=12;
cnt:=0;
else
cnt:=cnt+1;
SF_D<=x"31";
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=11;
end if;
when 12=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=13;
else
SF_D<=x"c0";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=12;
cnt:=cnt+1;
end if;

when 13=>
if cnt=1600 then
state:=14;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"c0";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=13;
end if;


when 14=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=15;
else
SF_D<=x"32";
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=14;
cnt:=cnt+1;
end if;

when 15=>
if cnt=1600 then
state:=8;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"32";
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=15;
end if;














end case;

end if;

end process;


end Behavioral;

