----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:34:19 12/16/2013 
-- Design Name: 
-- Module Name:    spi_test - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity spi_test is
port(
     miso   : IN     STD_LOGIC;                             --master in, slave out
     clk   : IN     STD_LOGIC;                             --master in, slave out
    sclk    : BUFFER STD_LOGIC;                             --spi clock
    ss_n    : BUFFER STD_LOGIC_vector(0 downto 0);   --slave select
    mosi    : OUT    STD_LOGIC

);



	 
end spi_test;

architecture Behavioral of spi_test is

--///////////////////////////////////////////////////////
component spi_master 
   GENERIC(
    slaves  : INTEGER := 8;  --number of spi slaves
    d_width : INTEGER := 8); --data bus width
  PORT(
    clock   : IN     STD_LOGIC;                             --system clock
    reset_n : IN     STD_LOGIC;                             --asynchronous reset
    enable  : IN     STD_LOGIC;                             --initiate transaction
    cpol    : IN     STD_LOGIC;                             --spi clock polarity
    cpha    : IN     STD_LOGIC;                             --spi clock phase
    cont    : IN     STD_LOGIC;                             --continuous mode command
    clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
    addr    : IN     INTEGER;                               --address of slave
    tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
    miso    : IN     STD_LOGIC;                             --master in, slave out
    sclk    : BUFFER STD_LOGIC;                             --spi clock
    ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
    mosi    : OUT    STD_LOGIC;                             --master out, slave in
    busy    : OUT    STD_LOGIC;                             --busy / data ready signal
    rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)
	 
	 ); --data received
END component;


signal   reset_n :      STD_LOGIC;                             --asynchronous reset
signal     enable  :     STD_LOGIC;                             --initiate transaction
signal     cpol    :      STD_LOGIC;                             --spi clock polarity
signal     cpha    :     STD_LOGIC;                             --spi clock phase
signal     cont    :      STD_LOGIC;                             --continuous mode command
signal    clk_div :      INTEGER;                               --system clock cycles per 1/2 period of sclk
signal     addr    :     INTEGER;                               --address of slave
signal     tx_data :     STD_LOGIC_VECTOR(7 DOWNTO 0);  --data to transmit
signal     busy    :     STD_LOGIC;                             --busy / data ready signal
signal     rx_data :     STD_LOGIC_VECTOR(7 DOWNTO 0); --data received






begin

u1: spi_master 
  GENERIC map(
    slaves  => 1,  --number of spi slaves
    d_width =>8) --data bus width
  PORT map(
    clock    =>  clk  ,                            --system clock
    reset_n  =>  reset_n   ,                             --asynchronous reset
    enable   => enable    ,                            --initiate transaction
    cpol     =>  cpol   ,                             --spi clock polarity
    cpha     =>  cpha    ,                             --spi clock phase
    cont     =>  cont   ,                           --continuous mode command
    clk_div => clk_div    ,                               --system clock cycles per 1/2 period of sclk
    addr     => addr   ,                               --address of slave
    tx_data  =>  tx_data  ,  --data to transmit
    miso     => miso   ,                            --master in, slave out
    sclk    => sclk   ,                          --spi clock
    ss_n     =>ss_n    ,   --slave select
    mosi    =>  mosi   ,                            --master out, slave in
    busy   =>  busy   ,                           --busy / data ready signal
    rx_data=>  rx_data   	 
	 
	 
	 
	 ); --data received


process(clk)
variable state:integer range 0 to 3:=0;
begin

if rising_edge(clk) then
case state is
when 0=>
reset_n<='1';
state:=1;
when 1=>
tx_data<=x"aa";
state:=2;
when 2=>
enable  <='1';                            --initiate transaction
cpol   <='1';                            --spi clock polarity
cpha   <='1'; 
clk_div<=2;
addr<=1;
state:=3;
cont<='1';
when 3=>
state:=0;

end case;
end if;
end process;












end Behavioral;

