Release 13.2 par O.61xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

MAZRAEH-PC::  Sun Dec 22 16:30:02 2013

par -w -intstyle ise -ol high -t 1 sample1_map.ncd sample1.ncd sample1.pcf 


Constraints file: sample1.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment C:\Xilinx\13.2\ISE_DS\ISE\.
   "sample1" is an NCD, version 3.2, device xc3s400, package pq208, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.39 2011-06-20".


Device Utilization Summary:

   Number of BSCANs                          1 out of 1     100%
   Number of BUFGMUXs                        3 out of 8      37%
   Number of DCMs                            1 out of 4      25%
   Number of External IOBs                  34 out of 141    24%
      Number of LOCed IOBs                  33 out of 34     97%

   Number of RAMB16s                         2 out of 16     12%
   Number of Slices                        380 out of 3584   10%
      Number of SLICEMs                     83 out of 1792    4%



Overall effort level (-ol):   High 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 1 secs 
Finished initial Timing Analysis.  REAL time: 1 secs 

WARNING:Par:288 - The signal nUSB_TXE_IBUF has no load.  PAR will not attempt to route this signal.

Starting Placer
Total REAL time at the beginning of Placer: 1 secs 
Total CPU  time at the beginning of Placer: 2 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:6c86dcb2) REAL time: 2 secs 

Phase 2.7  Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 34 IOs, 33 are locked and 1 are not locked. If you would like
   to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 
Phase 2.7  Design Feasibility Check (Checksum:6c86dcb2) REAL time: 2 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:ab1ac8f2) REAL time: 2 secs 

Phase 4.2  Initial Clock and IO Placement

Phase 4.2  Initial Clock and IO Placement (Checksum:f1220768) REAL time: 2 secs 

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:f1220768) REAL time: 2 secs 

Phase 6.8  Global Placement
............
..
Phase 6.8  Global Placement (Checksum:78aa8d4) REAL time: 3 secs 

Phase 7.5  Local Placement Optimization
Phase 7.5  Local Placement Optimization (Checksum:78aa8d4) REAL time: 3 secs 

Phase 8.18  Placement Optimization
Phase 8.18  Placement Optimization (Checksum:4c95770a) REAL time: 3 secs 

Phase 9.5  Local Placement Optimization
Phase 9.5  Local Placement Optimization (Checksum:4c95770a) REAL time: 3 secs 

Total REAL time to Placer completion: 3 secs 
Total CPU  time to Placer completion: 3 secs 
Writing design to file sample1.ncd



Starting Router


Phase  1  : 2611 unrouted;      REAL time: 4 secs 

Phase  2  : 1956 unrouted;      REAL time: 4 secs 

Phase  3  : 530 unrouted;      REAL time: 4 secs 

Phase  4  : 530 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 4 secs 

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 secs 

Updating file: sample1.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 5 secs 
WARNING:Route:455 - CLK Net:CONTROL<13> may have excessive skew because 
      1 CLK pins and 4 NON_CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 5 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|          CONTROL<0> |      BUFGMUX4| No   |  109 |  0.020     |  1.034      |
+---------------------+--------------+------+------+------------+-------------+
|            CLK0_OUT |      BUFGMUX3| No   |  194 |  0.060     |  1.074      |
+---------------------+--------------+------+------+------------+-------------+
|            CLK_IBUF |      BUFGMUX0| No   |   21 |  0.059     |  1.073      |
+---------------------+--------------+------+------+------------+-------------+
|         CONTROL<13> |         Local|      |    5 |  0.000     |  1.070      |
+---------------------+--------------+------+------+------------+-------------+
|chip_icon/U0/iUPDATE |              |      |      |            |             |
|                _OUT |         Local|      |    1 |  0.000     |  2.852      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP       |    10.261ns|     4.739ns|       0|           0
   TO TIMEGRP "J_CLK" 15 ns                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP       |    13.325ns|     1.675ns|       0|           0
   TO TIMEGRP "U_CLK" 15 ns                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns H | SETUP       |    14.106ns|    15.894ns|       0|           0
  IGH 50%                                   | HOLD        |     0.806ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_J_TO_D_path" TIG                 | SETUP       |         N/A|    10.889ns|     N/A|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_D_TO_J_path" TIG                 | SETUP       |         N/A|     6.898ns|     N/A|           0
----------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  260 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file sample1.ncd



PAR done!
