library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;

-- Generated from Simulink block "lab7_solution"

entity lab7_solution is
  port (
    ce_1: in std_logic; 
    ce_450: in std_logic; 
    ce_logic_450: in std_logic; 
    clk_1: in std_logic; 
    clk_450: in std_logic; 
    gateway_in: in std_logic_vector(7 downto 0); 
    fir_output: out std_logic_vector(7 downto 0)
  );
end lab7_solution;

architecture structural of lab7_solution is
  attribute core_generation_info: string;
  attribute core_generation_info of structural : architecture is "lab7_solution,sysgen_core,{clock_period=10.00000000,clocking=Clock_Enables,compilation=HDL_Netlist,sample_periods=1.00000000000 450.00000000000,testbench=1,total_blocks=53,xilinx_copyright_notice_block=1,xilinx_fdatool_interface_block=1,xilinx_fir_compiler_5_0_block=1,xilinx_gateway_in_block=1,xilinx_gateway_out_block=1,xilinx_register_block=2,xilinx_system_generator_block=1,}";

  signal ce_1_sg_x0: std_logic;
  signal ce_450_sg_x0: std_logic;
  signal ce_logic_450_sg_x0: std_logic;
  signal clk_1_sg_x0: std_logic;
  signal clk_450_sg_x0: std_logic;
  signal fir_compiler_5_0_dout_net: std_logic_vector(7 downto 0);
  signal fir_compiler_5_0_rdy_net: std_logic;
  signal fir_output_net: std_logic_vector(7 downto 0);
  signal gateway_in_net: std_logic_vector(7 downto 0);
  signal register1_q_net: std_logic_vector(7 downto 0);

begin
  ce_1_sg_x0 <= ce_1;
  ce_450_sg_x0 <= ce_450;
  ce_logic_450_sg_x0 <= ce_logic_450;
  clk_1_sg_x0 <= clk_1;
  clk_450_sg_x0 <= clk_450;
  gateway_in_net <= gateway_in;
  fir_output <= fir_output_net;

  fir_compiler_5_0: entity work.xlfir_compiler_055756ede3fb5e89fc74079c74ca9efd
    port map (
      ce => ce_1_sg_x0,
      ce_450 => ce_450_sg_x0,
      ce_logic_450 => ce_logic_450_sg_x0,
      clk => clk_1_sg_x0,
      clk_450 => clk_450_sg_x0,
      clk_logic_450 => clk_450_sg_x0,
      din => register1_q_net,
      src_ce => ce_450_sg_x0,
      src_clk => clk_450_sg_x0,
      dout => fir_compiler_5_0_dout_net,
      rdy => fir_compiler_5_0_rdy_net
    );

  register1: entity work.xlregister
    generic map (
      d_width => 8,
      init_value => b"00000000"
    )
    port map (
      ce => ce_450_sg_x0,
      clk => clk_450_sg_x0,
      d => gateway_in_net,
      en => "1",
      rst => "0",
      q => register1_q_net
    );

  register2: entity work.xlregister
    generic map (
      d_width => 8,
      init_value => b"00000000"
    )
    port map (
      ce => ce_450_sg_x0,
      clk => clk_450_sg_x0,
      d => fir_compiler_5_0_dout_net,
      en(0) => fir_compiler_5_0_rdy_net,
      rst => "0",
      q => fir_output_net
    );

end structural;
