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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:33:05 11/22/2013 
-- Design Name: 
-- Module Name:    sram_test - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sram_test is
port(
clk, reset: in std_logic;
---sram---
sram_data :inout std_logic_vector(7 downto 0);
sram_addr   : out std_logic_vector(18 downto 0);
sram_we_n, sram_oe_n: out std_logic;
sram_ce_n: out std_logic;
----lcd-------
 SF_D   : out std_logic_vector(7 downto 0);
 LCD_E  : out std_logic; 
 LCD_RS : out std_logic; 
 LCD_RW : out std_logic;
-----led-------------------------------


led:out std_logic_vector(7 downto 0):=x"00";
led_gnd:out std_logic



);
end sram_test;

architecture Behavioral of sram_test is
component sram_ctrl is
port(
clk, reset: in std_logic;
mem: in std_logic;
rw: in std_logic;
addr: in std_logic_vector(18 downto 0);
data_f2s: in std_logic_vector(7 downto 0);
ready: out std_logic;
data_s2f_r, data_s2f_ur:out std_logic_vector(7 downto 0);
ad: out std_logic_vector(18 downto 0);
we_n, oe_n: out std_logic;
dio: inout std_logic_vector(7 downto 0);
ce_n: out std_logic);

end component;

----------------------------
component ila
  PORT (
    CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
    CLK : IN STD_LOGIC;
    TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));

end component;
-------------------------------

component icon
  PORT (
    CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));

end component;
-----------------------------
signal mem :std_logic;
signal rw:std_logic;
signal addr:std_logic_vector(18 downto 0);
signal data_f2s :std_logic_vector(7 downto 0);
signal ready :std_logic;
signal data_s2f_r:std_logic_vector(7 downto 0);
signal data_s2f_ur:std_logic_vector(7 downto 0);

signal read_data:std_logic_vector(7 downto 0);


signal CONTROL:std_logic_vector(35 downto 0);
signal TRIG0:std_logic_vector(31 downto 0);

signal char1:std_logic_vector(7 downto 0);
signal char2:std_logic_vector(7 downto 0);



 

begin
led_gnd<='1';









u1:sram_ctrl 
port map(
clk=>clk ,
reset=>reset ,
mem=>mem ,
rw=>rw ,
addr=>addr ,
data_f2s=>data_f2s ,
ready=>ready ,
data_s2f_r=> data_s2f_r,
data_s2f_ur=>data_s2f_ur ,
ad=>sram_addr ,
we_n=>sram_we_n ,
oe_n=>sram_oe_n ,
dio=>sram_data  ,
ce_n=>sram_ce_n
);
-----------------------
u2 : ila
  port map (
    CONTROL => CONTROL,
    CLK => CLK,
    TRIG0 => TRIG0);
------------------------------
u3 : icon
  port map (
    CONTROL0 => CONTROL);







process(clk)
variable cnt:integer range 0 to 100:=0;
variable cnt2:integer range 0 to 40000000:=0;
variable state:integer range 0 to 8:=0;

begin
if rising_edge(clk) then

case state is





when 0=>
TRIG0(8)<='0';
mem<='1';
rw<='0';
state:=1;
when 1=>
TRIG0(8)<='0';
addr<="0000000000000000000";
data_f2s<=x"00";
state:=2;
when 2=>
TRIG0(8)<='0';
if cnt=3 then
cnt:=0;

state:=3;
else
cnt:=cnt+1;
state:=2;
end if;

when 3=>
if addr=99  then
state:=4;
else
addr<=addr+1;
data_f2s<=data_f2s+1;
state:=2;
end if;

when 4=>
TRIG0(8)<='0';
rw<='1';
state:=5;
when 5=>
TRIG0(8)<='0';
addr<="0000000000000000000";
read_data<=data_s2f_r;
state:=6;
when 6=>
TRIG0(8)<='0';
if cnt=3 then
cnt:=0;
state:=7;
else
cnt:=cnt+1;
state:=6;
end if;
when 7=>
if addr=99 then
addr<=(others=>'0');
state:=0;
else
addr<=addr+1;
read_data<=data_s2f_r;
state:=8;
end if;
when 8=>

if cnt2=38000000 then
cnt2:=0;
state:=7;
else
cnt2:=cnt2+1;
led<=not read_data;
state:=8;
if read_data(7 downto 4)<x"a" then

char1<=read_data(7 downto 4)+x"30";
TRIG0(7 downto 0)<=read_data(7 downto 4)+x"30";
else

char1<=read_data(7 downto 4)+x"37";
TRIG0(7 downto 0)<=read_data(7 downto 4)+x"37";
end if;

if read_data(3 downto 0)<x"a" then
TRIG0(16 downto 9)<=read_data(3 downto 0)+x"30";
char2<=read_data(3 downto 0)+x"30";

else 
TRIG0(16 downto 9)<=read_data(3 downto 0)+x"37";
char2<=read_data(3 downto 0)+x"37";
end if;

end if;
end case;
end if;
end process;



process(clk)
variable cnt:integer range 0 to 2000:=0;
variable state:integer range 11 to 26:=11;

begin
if rising_edge(clk) then

-------------------
--------------------
-------lcd-------------

case state is
when 11=>

if cnt=20 then
cnt:=0;
LCD_E  <='0';
state:=12;
else
cnt:=cnt+1;
SF_D<=x"38";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=11;

end if;

when 12=>
if cnt=1600 then
state:=13;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"38";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=12;
end if;

when 13=>
if cnt=20 then
cnt:=0;
LCD_E  <='0';
state:=14;
else
SF_D<=x"0c";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=13;
cnt:=cnt+1;
end if;

when 14=>
if cnt=1600 then
state:=15;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"0c";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=14;
end if;
when 15=>

if cnt=20 then
cnt:=0;
LCD_E <='0';
state:=16;
else
SF_D<=x"01";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=15;
cnt:=cnt+1;
end if;
when 16=>
if cnt=1600 then
state:=17;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"01";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=16;
end if;

when 17=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=18;
else
SF_D<=x"06";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=17;
cnt:=cnt+1;
end if;

when 18=>
if cnt=1600 then
state:=19;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"06";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=18;
end if;

when 19=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=20;
else
SF_D<=x"80";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=19;
cnt:=cnt+1;
end if;

when 20=>


if cnt=1600 then
state:=21;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"80";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=20;
end if;








when 21=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=22;
else
SF_D<=char1;
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=21;
cnt:=cnt+1;
end if;

when 22=>
if cnt=1600 then
state:=23;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=char1;
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=22;
end if;

when 23=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=24;
else
SF_D<=x"81";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=23;
cnt:=cnt+1;
end if;

when 24=>
if cnt=1600 then
state:=25;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"81";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=24;
end if;


when 25=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=26;
else
SF_D<=char2;
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=25;
cnt:=cnt+1;
end if;

when 26=>
if cnt=1600 then
state:=19;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=char2;
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=26;
end if;






















end case;
end if;
end process;













end Behavioral;

