----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:02:37 12/23/2013 
-- Design Name: 
-- Module Name:    vga - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vga is
port(
clk:in std_logic;
reset:in std_logic;

RGB:out std_logic_vector(2 downto 0);
hsync :out std_logic;
vsync :out std_logic

);

end vga;

architecture Behavioral of vga is
 

constant           H_PIXELS      :integer := 806;
constant           H_FRONTPORCH  :integer :=37; 
constant           H_SYNCTIME    :integer  :=128; 
constant           H_BACKPORCH   :integer := 85; 
constant           H_SYNCSTART   :integer  :=843; -- H_PIXELS + H_FRONTPORCH,
constant           H_SYNCEND     :integer  :=971; -- H_SYNCSTART + H_SYNCTIME,
constant           H_PERIOD      :integer  :=1056; --H_SYNCEND + H_BACKPORCH,
 --Vertical timing constants
constant          V_LINES       :integer  :=604;          
--constant          V_FRONTPORCH  :integer range 0 to -1:=0; 
constant         V_SYNCTIME    :integer  :=4; 
constant         V_BACKPORCH   :integer  :=21; 
constant         V_SYNCSTART   :integer  :=603;--V_LINES + V_FRONTPORCH,
constant         V_SYNCEND     :integer  :=607; -- V_SYNCSTART + V_SYNCTIME,
constant        V_PERIOD      :integer    :=628;--V_SYNCEND + V_BACKPORCH;
-------------------------
   
 signal hcnt,vcnt:integer range 0 to 1500:=0;
 signal enable,hsyncint:std_logic;





begin
process(CLK,reset)
begin


if reset='0' then
 hcnt <= 0;
elsif rising_edge(CLK) then

if(hcnt<h_PERIOD) then
 hcnt <= hcnt + 1; 
 else
 hcnt <= 0;
end if;






end if;
end process;






--------------------------------------------------------------------------------
----Internal horizontal synchronization pulse generation (negative polarity)----
--------------------------------------------------------------------------------

process(clk,reset)
begin

--
if reset='0' then
 hsyncint<= '1';
 
elsif rising_edge(CLK) then
hsync <= hsyncint;
 
if(hcnt >= h_SYNCSTART and hcnt <h_SYNCEND) then
 hsyncint <='0'; 
--hsync<='1';
else
 hsyncint<= '1';
--hsync<='0';  
end if;

end if;

end process;
-------------------------------------
----Vertical counter of lines--------
-------------------------------------
process(reset,hsyncint)
begin


if reset='0' then
vcnt<=0;
elsif rising_edge(hsyncint)  then
 
if(vcnt < v_PERIOD) then
vcnt <=vcnt + 1;
else
vcnt<=0;
end if;
end if;



end process;
------------------------------------------------------------------------
---Vertical synchronization pulse generation (negative polarity)--------
------------------------------------------------------------------------

process(hsyncint,reset)
begin


if reset='0' then
vsync <='1';
elsif rising_edge(hsyncint)  then
 
if(vcnt >= v_SYNCSTART and vcnt < v_SYNCEND) then
vsync <='0';
else 
vsync <='1';

end if;
end if;
end process;
---------------------------------------------
------Enabling of color outputs--------------
---------------------------------------------
process(CLK,reset)
begin
if reset='0' then
 enable<='0';
elsif rising_edge(CLK) then

if(hcnt >= H_PIXELS or vcnt >= V_LINES) then
  enable<='0';  
 else
  enable<='1'; 
end if;

end if;

end process;
---------------------------------------------------------------------------
---Output image generation (horizontal or vertical color stripes)----------
---------------------------------------------------------------------------
process(enable ,vcnt,reset,hcnt)
begin

if reset='0' then
rgb <= "000";
elsif rising_edge(CLK) then

if enable='0' then

  rgb<="000";
 else
if(hcnt<100) then
   rgb<="001";
elsif(hcnt<200) then
    rgb<="010";
elsif(hcnt<300) then
    rgb<="011";
elsif(hcnt<400)  then
    rgb<="100";
elsif(hcnt<500)  then
     rgb<="101";
elsif(hcnt<600) then
      rgb<="110";
elsif(hcnt<700) then
      rgb<="111";
end if;







end if;
end if;

end process;

end Behavioral;