library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity usart is
port(
  
             clk 					: 	in  	std_logic;
				serial_in 			: 	in  	std_logic;
				serial_out 			: 	out  	std_logic
				
  
  );
end usart;

architecture Behavioral of usart is
      
		
		
		component SERIAL_PACK 
                generic(	oscillator_clk		:	integer		:=50000000;--7372800;--
				               baud_rate			:	integer		:=9600;
				               parity_enable		:	std_logic	:='1';
				                parity_type		:	std_logic	:='0'	-- Even='0' , Odd='1'
				                                 );
                 port ( 	
				                clk 					: 	in  	std_logic;
				                serial_in 			: 	in  	std_logic;
				                serial_out 			: 	out  	std_logic;
				                received_data		:	out	std_logic_vector(7 downto 0):=(others=>'0');
			                   send_data			:	in		std_logic_vector(7 downto 0);
				                receive_enable		:	in		std_logic;
				                send_enable			:	in		std_logic;
				                receive_flag		:	out	std_logic:='0';
			                   send_flag			:	inout std_logic:='0';
			                   receive_error		:	out	std_logic:='0'
				); 	
	      		
end component;	
  
  
   signal read_data:	std_logic_vector(7 downto 0);
	signal send_data	:	std_logic_vector(7 downto 0);
	signal receive_en	:	std_logic;
	signal send_en	:	std_logic;
	signal receive_flage	:	std_logic;
	signal send_flage	:	std_logic;

	
	 
  
  
  
 begin
 
txrx:entity SERIAL_PACK  
	generic map(oscillator_clk		=>50000000,
				baud_rate			=>9600,
				parity_enable		=>'0',
				parity_type			=>'0'	
				) 
    port map( 	
				clk 		=>clk,			
				serial_in =>serial_in,	 	
				serial_out =>serial_out,			
				received_data =>	read_data,	
				send_data	=>send_data,			
				receive_enable	=>receive_en,	
				send_enable	=>send_en,			
				receive_flag	=>receive_flage,		
				send_flag	=>send_flage,			
				receive_error		=> open--:	
				);





 
--------------------------------------------------------	---		
	
	
				
				
				
				
				

---------------------------------------------------------
process (CLK)
variable state: integer range 0 to 23:=0;	
variable cnt: integer range 0 to 40000000:=0;	
		begin
		
	if rising_edge(CLK) then 

	
case state is

	when 0 =>
	send_en<='1';
	send_data <= x"4E";
	if send_flage='0' then
	state:=1;
		else
	 state:=0;
	end if;
	
	when 1 =>
 send_en<='0';
	state:=2;	
when 2 =>
            send_en<='1';
				send_data <= x"49";
				if send_flage='0' then
				state:=3;
			else
			state:=2;
			end if;
	when 3 =>
	send_en<='0';
	state:=4;

When 4 =>
            send_en<='1';
				send_data <= x"52";
				if send_flage='0' then
				state:=5;
			else
			state:=4;
			end if;
	when 5 =>
	send_en<='0';
	state:=6;

When 6 =>
            send_en<='1';
				send_data <= x"41";
				if send_flage='0' then
				state:=7;
			else
			state:=6;
			end if;
	when 7 =>
	send_en<='0';
	state:=8;
	
	When 8 =>
            send_en<='1';
				send_data <= x"20";
				if send_flage='0' then
				state:=9;
			else
			state:=8;
			end if;
	when 9 =>
	send_en<='0';
	state:=10;
When 10=>
            send_en<='1';
				send_data <= x"53";
				if send_flage='0' then
				state:=11;
			else
			state:=10;
			end if;
	when 11 =>
	send_en<='0';
	state:=12;
	
	When 12 =>
            send_en<='1';
				send_data <= x"59";
				if send_flage='0' then
				state:=13;
			else
			state:=12;
			end if;
	when 13 =>
	send_en<='0';
	state:=14;
	When 14 =>
            send_en<='1';
				send_data <= x"53";
				if send_flage='0' then
				state:=15;
			else
			state:=14;
			end if;
	when 15 =>
	send_en<='0';
	state:=16;
When 16 =>
            send_en<='1';
				send_data <= x"54";
				if send_flage='0' then
				state:=17;
			else
			state:=16;
			end if;
	when 17 =>
	send_en<='0';
	state:=18;
When 18 =>
            send_en<='1';
				send_data <= x"45";
				if send_flage='0' then
				state:=19;
			else
			state:=18;
			end if;
	when 19 =>
	send_en<='0';
	state:=20;
When 20 =>
            send_en<='1';
				send_data <= x"4D";
				if send_flage='0' then
				state:=21;
			else
			state:=20;
			end if;
	when 21 =>
	send_en<='0';
	state:=22;	
	When 22 =>
            send_en<='1';
				send_data <= x"0A";
				if send_flage='0' then
				state:=23;
			else
			state:=22;
			end if;
	when 23 =>
	if cnt=20000000 then
	cnt:=0;
	state:=0;
	
	else
	send_en<='0';
	state:=23;	
	cnt:=cnt+1;
	end if;

	
			end case;
	
	end if;
	
				
		end process;	
end Behavioral;
--
