test Project Status (12/18/2013 - 18:56:15)
Project File: | ps22.xise | Parser Errors: | No Errors
Module Name: | PS2_Ctrl | Implementation State: | Synthesized
Target Device: | xc3s400-4pq208 |

- Errors:

Product Version: | ISE 13.2 |

- Warnings:

Design Goal: | Balanced |

- Routing Results:

Design Strategy: | Xilinx Default (unlocked) |

- Timing Constraints:

Environment: | System Settings |

- Final Timing Score:

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slices | 27 | 3584 | 0%
Number of Slice Flip Flops | 36 | 7168 | 0%
Number of 4 input LUTs | 26 | 7168 | 0%
Number of bonded IOBs | 15 | 141 | 10%
Number of GCLKs | 1 | 8 | 12%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Wed Dec 18 18:35:43 2013 |  |  |
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | Wed Dec 18 18:55:57 2013
WebTalk Log File | Current | Wed Dec 18 18:56:14 2013

Date Generated: 12/18/2013 - 18:56:15