
open(PIDFILE, '> pidfile.txt') || die 'Couldn\'t write process ID to file.';
print PIDFILE "$$\n";
close(PIDFILE);

eval {
  # Call script(s).
  my $instrs;
  my $results = [];
$ENV{'SYSGEN'} = 'C:/Xilinx/13.2/ISE_DS/ISE/sysgen';
  use Sg;
  $instrs = {
    'HDLCodeGenStatus' => 0.0,
    'HDL_PATH' => 'C:/Users/mazraeh/Desktop/lab7/solution',
    'TEMP' => 'C:/Users/mazraeh/AppData/Local/Temp',
    'TMP' => 'C:/Users/mazraeh/AppData/Local/Temp',
    'Temp' => 'C:/Users/mazraeh/AppData/Local/Temp',
    'Tmp' => 'C:/Users/mazraeh/AppData/Local/Temp',
    'base_system_period_hardware' => 10.0,
    'base_system_period_simulink' => 1.111111111111111E-6,
    'block_icon_display' => 'Default',
    'block_type' => 'sysgen',
    'block_version' => '8.2',
    'ce_clr' => 0.0,
    'clock_domain' => 'default',
    'clock_loc' => '',
    'clock_wrapper' => 'Clock Enables',
    'compilation' => 'HDL Netlist',
    'compilation_lut' => {
      'keys' => [
        'HDL Netlist',
        'Timing Analysis',
        'Bitstream',
      ],
      'values' => [
        'target1',
        'target2',
        'target3',
      ],
    },
    'compilation_target' => 'HDL Netlist',
    'core_generation' => 1.0,
    'core_generation_sgadvanced' => '',
    'core_is_deployed' => 0.0,
    'coregen_core_generation_tmpdir' => 'C:/Users/mazraeh/AppData/Local/Temp/sysgentmp-mazraeh/cg_wk/cd733faa138efcff4',
    'coregen_part_family' => 'spartan3',
    'createTestbench' => 1,
    'create_interface_document' => 'off',
    'dbl_ovrd' => -1.0,
    'dbl_ovrd_sgadvanced' => '',
    'dcm_input_clock_period' => 100.0,
    'deprecated_control' => 'off',
    'deprecated_control_sgadvanced' => '',
    'design' => 'lab7_solution',
    'design_full_path' => 'C:\\Users\\mazraeh\\Desktop\\lab7\\solution\\lab7_solution.mdl',
    'device' => 'xc3s400-4pq208',
    'device_speed' => '-4',
    'directory' => 'C:/Users/mazraeh/Desktop/lab7/solution',
    'dsp_cache_root_path' => 'C:/Users/mazraeh/AppData/Local/Temp/sysgentmp-mazraeh',
    'eval_field' => '0',
    'fileDeliveryDefaults' => [
      [
        '(?i)\\.vhd$',
        { 'fileName' => 'C:/Users/mazraeh/Desktop/lab7/solution/sysgen/perl_results.vhd', },
      ],
      [
        '(?i)\\.v$',
        { 'fileName' => 'C:/Users/mazraeh/Desktop/lab7/solution/sysgen/perl_results.v', },
      ],
    ],
    'fxdptinstalled' => 1.0,
    'generateUsing71FrontEnd' => 1,
    'generating_island_subsystem_handle' => 2070.0001220703125,
    'generating_subsystem_handle' => 2070.0001220703125,
    'generation_directory' => 'C:/Users/mazraeh/Desktop/lab7/solution',
    'has_advanced_control' => '0',
    'hdlDir' => 'C:/Xilinx/13.2/ISE_DS/ISE/sysgen/hdl',
    'hdlKind' => 'vhdl',
    'hdl_path' => 'C:/Users/mazraeh/Desktop/lab7/solution',
    'incr_netlist' => 'off',
    'incr_netlist_sgadvanced' => '',
    'infoedit' => ' System Generator',
    'isdeployed' => 0,
    'ise_version' => '13.2i',
    'master_sysgen_token_handle' => 2071.0001220703125,
    'matlab' => 'C:/Program Files/MATLAB/R2011a',
    'matlab_fixedpoint' => 1.0,
    'mdlHandle' => 2070.0001220703125,
    'mdlPath' => 'C:/Users/mazraeh/Desktop/lab7/solution/lab7_solution.mdl',
    'modelDiagnostics' => [
      {
        'count' => 53.0,
        'isMask' => 0.0,
        'type' => 'lab7_solution Total blocks',
      },
      {
        'count' => 1.0,
        'isMask' => 0.0,
        'type' => 'DataTypeConversion',
      },
      {
        'count' => 2.0,
        'isMask' => 0.0,
        'type' => 'DiscretePulseGenerator',
      },
      {
        'count' => 1.0,
        'isMask' => 0.0,
        'type' => 'DotProduct',
      },
      {
        'count' => 8.0,
        'isMask' => 0.0,
        'type' => 'Inport',
      },
      {
        'count' => 1.0,
        'isMask' => 0.0,
        'type' => 'M-S-Function',
      },
      {
        'count' => 2.0,
        'isMask' => 0.0,
        'type' => 'Math',
      },
      {
        'count' => 1.0,
        'isMask' => 0.0,
        'type' => 'Mux',
      },
      {
        'count' => 7.0,
        'isMask' => 0.0,
        'type' => 'Outport',
      },
      {
        'count' => 2.0,
        'isMask' => 0.0,
        'type' => 'Probe',
      },
      {
        'count' => 2.0,
        'isMask' => 0.0,
        'type' => 'Product',
      },
      {
        'count' => 13.0,
        'isMask' => 0.0,
        'type' => 'S-Function',
      },
      {
        'count' => 1.0,
        'isMask' => 0.0,
        'type' => 'Selector',
      },
      {
        'count' => 9.0,
        'isMask' => 0.0,
        'type' => 'SubSystem',
      },
      {
        'count' => 3.0,
        'isMask' => 0.0,
        'type' => 'Terminator',
      },
      {
        'count' => 4.0,
        'isMask' => 1.0,
        'type' => 'Check Signal Attributes',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Digital Filter',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'FFT',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Frame Scope',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Magnitude FFT',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Periodogram',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Replaceable Contents',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Spectrum Scope',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Submatrix',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Window Function',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Xilinx Copyright Notice Block',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Xilinx FDATool Interface Block',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Xilinx FIR Compiler 5.0 Block',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Xilinx Gateway In Block',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Xilinx Gateway Out Block',
      },
      {
        'count' => 2.0,
        'isMask' => 1.0,
        'type' => 'Xilinx Register Block',
      },
      {
        'count' => 1.0,
        'isMask' => 1.0,
        'type' => 'Xilinx System Generator Block',
      },
    ],
    'model_globals_initialized' => 1.0,
    'model_path' => 'C:/Users/mazraeh/Desktop/lab7/solution/lab7_solution.mdl',
    'myxilinx' => 'C:/Xilinx/13.2/ISE_DS/ISE',
    'ngc_files' => [ 'xlpersistentdff.ngc', ],
    'num_sim_cycles' => '90000',
    'package' => 'pq208',
    'part' => 'xc3s400',
    'partFamily' => 'spartan3',
    'port_data_types_enabled' => 0.0,
    'preserve_hierarchy' => 0.0,
    'proj_type' => 'Project Navigator',
    'run_coregen' => 'off',
    'run_coregen_sgadvanced' => '',
    'sample_time_colors_enabled' => 0.0,
    'sampletimecolors' => 0.0,
    'sg_blockgui_xml' => '<!--  *  Copyright (c) 2005, Xilinx, Inc.  All Rights Reserved.            --><!--  *  Reproduction or reuse, in any form, without the explicit written  --><!--  *  consent of Xilinx, Inc., is strictly prohibited.                  --><sysgenblock has_userdata="true" tag="genX" block_type="sysgen" simulinkname=" System Generator" >
 <icon width="51" bg_color="beige" height="50" caption_format="System\\nGenerator" wmark_color="red" />
 <callbacks DeleteFcn="xlSysgenGUI(\'delete\', gcs, gcbh);" OpenFcn="xlSysgenGUI(\'startup\',gcs,gcbh)" ModelCloseFcn="xlSysgenGUI(\'Close\',gcs,gcbh)" PostSaveFcn="xlSysgenGUI(\'Save\')" />
 <libraries>
  <library name="xbsIndex" />
  <library name="xbsBasic" />
  <library name="xbsTools" />
 </libraries>
 <subsystem_model file="system_generator_subsystem.mdl" />
 <blockgui label="Xilinx System Generator" >
  <editbox evaluate="false" multi_line="true" name="infoedit" read_only="true" default=" System Generator" />
  <editbox evaluate="false" name="xilinxfamily" default="Virtex4" label="Xilinx family" />
  <editbox evaluate="false" name="part" default="xc4vsx35" label="Part" />
  <editbox evaluate="false" name="speed" default="-10" label="Speed" />
  <editbox evaluate="false" name="package" default="ff668" label="Package" />
  <listbox evaluate="true" name="synthesis_tool" default="XST" label="Synthesis tool" >
   <item value="Spectrum" />
   <item value="Synplify" />
   <item value="Synplify Pro" />
   <item value="XST" />
   <item value="Precision" />
  </listbox>
  <editbox evaluate="false" name="directory" default="./netlist" label="Target directory" />
  <checkbox evaluate="true" name="testbench" default="off" label="Testbench" />
  <editbox evaluate="true" name="simulink_period" default="1" label="Simulink period" />
  <editbox evaluate="true" name="sysclk_period" default="10" label="System clock period" />
  <checkbox evaluate="true" name="incr_netlist" default="off" label="Incremental netlisting" />
  <listbox evaluate="true" name="trim_vbits" default="Everywhere in SubSystem" label="Trim valid bits" >
   <item value="According to Block Masks" />
   <item value="Everywhere in SubSystem" />
   <item value="No Where in SubSystem" />
  </listbox>
  <listbox evaluate="true" name="dbl_ovrd" default="According to Block Masks" label="Override with doubles" >
   <item value="According to Block Masks" />
   <item value="Everywhere in SubSystem" />
   <item value="No Where in SubSystem" />
  </listbox>
  <listbox evaluate="true" name="core_generation" default="According to Block Masks" label="Generate cores" >
   <item value="According to Block Masks" />
   <item value="Everywhere Available" />
   <item value="Not Needed - Already Generated" />
  </listbox>
  <checkbox evaluate="true" name="run_coregen" default="off" label="Run CoreGen" />
  <checkbox evaluate="true" name="deprecated_control" default="off" label="Show deprecated controls" />
  <hiddenvar evaluate="true" name="eval_field" default="0" />
 </blockgui>
</sysgenblock>
',
    'sg_icon_stat' => '51,50,-1,-1,red,beige,0,07734',
    'sg_list_contents' => '',
    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
patch([0 51 51 0 ],[0 0 50 50 ],[0.93 0.92 0.86]);
patch([12 4 16 4 12 25 29 33 47 36 25 17 29 17 25 36 47 33 29 25 12 ],[5 13 25 37 45 45 41 45 45 34 45 37 25 13 5 16 5 5 9 5 5 ],[0.6 0.2 0.25]);
plot([0 0 51 51 0 ],[0 50 50 0 0 ]);
fprintf(\'\',\'COMMENT: end icon graphics\');
fprintf(\'\',\'COMMENT: begin icon text\');
fprintf(\'\',\'COMMENT: end icon text\');
',
    'sg_version' => '',
    'sggui_pos' => '-1,-1,-1,-1',
    'simulation_island_subsystem_handle' => 2070.0001220703125,
    'simulink_accelerator_running' => 0.0,
    'simulink_debugger_running' => 0.0,
    'simulink_period' => 1.111111111111111E-6,
    'speed' => '-4',
    'synthesisTool' => 'XST',
    'synthesis_language' => 'vhdl',
    'synthesis_tool' => 'XST',
    'synthesis_tool_sgadvanced' => '',
    'sysclk_period' => 10.0,
    'sysgen' => 'C:/Xilinx/13.2/ISE_DS/ISE/sysgen',
    'sysgenRoot' => 'C:/Xilinx/13.2/ISE_DS/ISE/sysgen',
    'sysgenTokenSettings' => {
      'base_system_period_hardware' => 10.0,
      'base_system_period_simulink' => 1.111111111111111E-6,
      'block_icon_display' => 'Default',
      'block_type' => 'sysgen',
      'block_version' => '8.2',
      'ce_clr' => 0.0,
      'clock_loc' => '',
      'clock_wrapper' => 'Clock Enables',
      'compilation' => 'HDL Netlist',
      'compilation_lut' => {
        'keys' => [
          'HDL Netlist',
          'Timing Analysis',
          'Bitstream',
        ],
        'values' => [
          'target1',
          'target2',
          'target3',
        ],
      },
      'core_generation' => 1.0,
      'core_generation_sgadvanced' => '',
      'coregen_part_family' => 'spartan3',
      'create_interface_document' => 'off',
      'dbl_ovrd' => -1.0,
      'dbl_ovrd_sgadvanced' => '',
      'dcm_input_clock_period' => 100.0,
      'deprecated_control' => 'off',
      'deprecated_control_sgadvanced' => '',
      'directory' => 'C:/Users/mazraeh/Desktop/lab7/solution',
      'eval_field' => '0',
      'has_advanced_control' => '0',
      'incr_netlist' => 'off',
      'incr_netlist_sgadvanced' => '',
      'infoedit' => ' System Generator',
      'master_sysgen_token_handle' => 2071.0001220703125,
      'package' => 'pq208',
      'part' => 'xc3s400',
      'preserve_hierarchy' => 0.0,
      'proj_type' => 'Project Navigator',
      'run_coregen' => 'off',
      'run_coregen_sgadvanced' => '',
      'sg_blockgui_xml' => '<!--  *  Copyright (c) 2005, Xilinx, Inc.  All Rights Reserved.            --><!--  *  Reproduction or reuse, in any form, without the explicit written  --><!--  *  consent of Xilinx, Inc., is strictly prohibited.                  --><sysgenblock has_userdata="true" tag="genX" block_type="sysgen" simulinkname=" System Generator" >
 <icon width="51" bg_color="beige" height="50" caption_format="System\\nGenerator" wmark_color="red" />
 <callbacks DeleteFcn="xlSysgenGUI(\'delete\', gcs, gcbh);" OpenFcn="xlSysgenGUI(\'startup\',gcs,gcbh)" ModelCloseFcn="xlSysgenGUI(\'Close\',gcs,gcbh)" PostSaveFcn="xlSysgenGUI(\'Save\')" />
 <libraries>
  <library name="xbsIndex" />
  <library name="xbsBasic" />
  <library name="xbsTools" />
 </libraries>
 <subsystem_model file="system_generator_subsystem.mdl" />
 <blockgui label="Xilinx System Generator" >
  <editbox evaluate="false" multi_line="true" name="infoedit" read_only="true" default=" System Generator" />
  <editbox evaluate="false" name="xilinxfamily" default="Virtex4" label="Xilinx family" />
  <editbox evaluate="false" name="part" default="xc4vsx35" label="Part" />
  <editbox evaluate="false" name="speed" default="-10" label="Speed" />
  <editbox evaluate="false" name="package" default="ff668" label="Package" />
  <listbox evaluate="true" name="synthesis_tool" default="XST" label="Synthesis tool" >
   <item value="Spectrum" />
   <item value="Synplify" />
   <item value="Synplify Pro" />
   <item value="XST" />
   <item value="Precision" />
  </listbox>
  <editbox evaluate="false" name="directory" default="./netlist" label="Target directory" />
  <checkbox evaluate="true" name="testbench" default="off" label="Testbench" />
  <editbox evaluate="true" name="simulink_period" default="1" label="Simulink period" />
  <editbox evaluate="true" name="sysclk_period" default="10" label="System clock period" />
  <checkbox evaluate="true" name="incr_netlist" default="off" label="Incremental netlisting" />
  <listbox evaluate="true" name="trim_vbits" default="Everywhere in SubSystem" label="Trim valid bits" >
   <item value="According to Block Masks" />
   <item value="Everywhere in SubSystem" />
   <item value="No Where in SubSystem" />
  </listbox>
  <listbox evaluate="true" name="dbl_ovrd" default="According to Block Masks" label="Override with doubles" >
   <item value="According to Block Masks" />
   <item value="Everywhere in SubSystem" />
   <item value="No Where in SubSystem" />
  </listbox>
  <listbox evaluate="true" name="core_generation" default="According to Block Masks" label="Generate cores" >
   <item value="According to Block Masks" />
   <item value="Everywhere Available" />
   <item value="Not Needed - Already Generated" />
  </listbox>
  <checkbox evaluate="true" name="run_coregen" default="off" label="Run CoreGen" />
  <checkbox evaluate="true" name="deprecated_control" default="off" label="Show deprecated controls" />
  <hiddenvar evaluate="true" name="eval_field" default="0" />
 </blockgui>
</sysgenblock>
',
      'sg_icon_stat' => '51,50,-1,-1,red,beige,0,07734',
      'sg_list_contents' => '',
      'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
patch([0 51 51 0 ],[0 0 50 50 ],[0.93 0.92 0.86]);
patch([12 4 16 4 12 25 29 33 47 36 25 17 29 17 25 36 47 33 29 25 12 ],[5 13 25 37 45 45 41 45 45 34 45 37 25 13 5 16 5 5 9 5 5 ],[0.6 0.2 0.25]);
plot([0 0 51 51 0 ],[0 50 50 0 0 ]);
fprintf(\'\',\'COMMENT: end icon graphics\');
fprintf(\'\',\'COMMENT: begin icon text\');
fprintf(\'\',\'COMMENT: end icon text\');
',
      'sggui_pos' => '-1,-1,-1,-1',
      'simulation_island_subsystem_handle' => 2070.0001220703125,
      'simulink_period' => 1.111111111111111E-6,
      'speed' => '-4',
      'synthesis_language' => 'vhdl',
      'synthesis_tool' => 'XST',
      'synthesis_tool_sgadvanced' => '',
      'sysclk_period' => 10.0,
      'testbench' => 1,
      'testbench_sgadvanced' => '',
      'trim_vbits' => 1.0,
      'trim_vbits_sgadvanced' => '',
      'xilinx_device' => 'xc3s400-4pq208',
      'xilinxfamily' => 'spartan3',
    },
    'sysgen_Root' => 'C:/Xilinx/13.2/ISE_DS/ISE/sysgen',
    'systemClockPeriod' => 10.0,
    'tempdir' => 'C:/Users/mazraeh/AppData/Local/Temp',
    'testbench' => 1,
    'testbench_sgadvanced' => '',
    'tmpDir' => 'C:/Users/mazraeh/Desktop/lab7/solution/sysgen',
    'trim_vbits' => 1.0,
    'trim_vbits_sgadvanced' => '',
    'use_strict_names' => 1,
    'user_tips_enabled' => 0.0,
    'usertemp' => 'C:/Users/mazraeh/AppData/Local/Temp/sysgentmp-mazraeh',
    'using71Netlister' => 1,
    'verilog_files' => [
      'conv_pkg.v',
      'synth_reg.v',
      'synth_reg_w_init.v',
      'convert_type.v',
    ],
    'version' => '',
    'vhdl_files' => [
      'conv_pkg.vhd',
      'synth_reg.vhd',
      'synth_reg_w_init.vhd',
    ],
    'vsimtime' => '990275.000000 ns',
    'xilinx' => 'C:/Xilinx/13.2/ISE_DS/ISE',
    'xilinx_device' => 'xc3s400-4pq208',
    'xilinx_family' => 'spartan3',
    'xilinx_package' => 'pq208',
    'xilinx_part' => 'xc3s400',
    'xilinxdevice' => 'xc3s400-4pq208',
    'xilinxfamily' => 'spartan3',
    'xilinxpart' => 'xc3s400',
  };
  push(@$results, &Sg::setAttributes($instrs));
  use SgDeliverFile;
  $instrs = {
    'collaborationName' => 'conv_pkg.vhd',
    'sourceFile' => 'hdl/conv_pkg.vhd',
    'templateKeyValues' => {},
  };
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
  $instrs = {
    'collaborationName' => 'synth_reg.vhd',
    'sourceFile' => 'hdl/synth_reg.vhd',
    'templateKeyValues' => {},
  };
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
  $instrs = {
    'collaborationName' => 'synth_reg_w_init.vhd',
    'sourceFile' => 'hdl/synth_reg_w_init.vhd',
    'templateKeyValues' => {},
  };
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
  $instrs = {
    'collaborationName' => 'xlpersistentdff.ngc',
    'sourceFile' => 'hdl/xlpersistentdff.ngc',
    'templateKeyValues' => {},
  };
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
  $instrs = {
    'entity_declaration_hash' => '7f9d93ac57e81265a371f4fbc426588c',
    'sourceFile' => 'C:/Xilinx/13.2/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
  };
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
  $instrs = {
    'entity_declaration_hash' => '93ed897e2fce0b3df1d7a54ffafd260a',
    'sourceFile' => 'C:/Xilinx/13.2/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
  };
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
  use SgGenerateCores;
  $instrs = [
    'SELECT FIR_Compiler spartan3 Xilinx,_Inc. 5.0',
    '# 13.2_O.61xd',
    '# DEVICE spartan3',
    '# VHDL',
    'CSET allow_rounding_approximation = false',
    'CSET bestprecision = false',
    'CSET chan_in_adv = 0',
    'CSET clock_frequency = 250',
    'CSET coefficient_buffer_type = Automatic',
    'CSET coefficient_file = no_coe_file_loaded',
    'CSET coefficient_fractional_bits = 0',
    'CSET coefficient_reload = false',
    'CSET coefficient_sets = 1',
    'CSET coefficient_sign = Signed',
    'CSET coefficient_structure = Inferred',
    'CSET coefficient_width = 8',
    'CSET coefficientsource = Vector',
    'CSET coefficientvector = 7.9385295169e-009,1.14280237898e-010,-1.84841144125e-008,-6.31791900603e-009,4.29518538325e-008,5.04647997664e-008,-1.71363013338e-007,-2.54096064945e-007,6.74708926285e-007,1.0015741889e-006,-2.3119760296e-006,-3.33322489346e-006,6.95132189245e-006,9.73227933463e-006,-1.87171444784e-005,-2.55309888626e-005,4.58956869246e-005,6.11753668782e-005,-0.000103801084834,-0.000135532745748,0.00021869149144,0.000280288872147,-0.000432643453495,-0.000545295251289,0.000809118068074,0.00100460417493,-0.00143895338906,-0.00176309145516,0.00244699412589,0.0029644124848,-0.00400105627968,-0.00480333113525,0.00632855355295,0.00755102652232,-0.00975493569479,-0.0116162606532,0.0148021876404,0.0177079045403,-0.0224650766163,-0.0273219824641,0.0351190346847,0.0445612342671,-0.0605760435769,-0.086728783146,0.148619519409,0.4491980283,0.4491980283,0.148619519409,-0.086728783146,-0.0605760435769,0.0445612342671,0.0351190346847,-0.0273219824641,-0.0224650766163,0.0177079045403,0.0148021876404,-0.0116162606532,-0.00975493569479,0.00755102652232,0.00632855355295,-0.00480333113525,-0.00400105627968,0.0029644124848,0.00244699412589,-0.00176309145516,-0.00143895338906,0.00100460417493,0.000809118068074,-0.000545295251289,-0.000432643453495,0.000280288872147,0.00021869149144,-0.000135532745748,-0.000103801084834,6.11753668782e-005,4.58956869246e-005,-2.55309888626e-005,-1.87171444784e-005,9.73227933463e-006,6.95132189245e-006,-3.33322489346e-006,-2.3119760296e-006,1.0015741889e-006,6.74708926285e-007,-2.54096064945e-007,-1.71363013338e-007,5.04647997664e-008,4.29518538325e-008,-6.31791900603e-009,-1.84841144125e-008,1.14280237898e-010,7.9385295169e-009',
    'CSET columnconfig = 1',
    'CSET data_buffer_type = Automatic',
    'CSET data_fractional_bits = 7',
    'CSET data_sign = Signed',
    'CSET data_width = 8',
    'CSET decimation_rate = 1',
    'CSET displayreloadorder = false',
    'CSET filter_architecture = Systolic_Multiply_Accumulate',
    'CSET filter_selection = 1',
    'CSET filter_type = Single_Rate',
    'CSET gui_behaviour = Coregen',
    'CSET hardwareoversamplingrate = 1',
    'CSET has_ce = true',
    'CSET has_data_valid = false',
    'CSET has_nd = true',
    'CSET has_sclr = false',
    'CSET input_buffer_type = Automatic',
    'CSET inter_column_pipe_length = 4',
    'CSET interpolation_rate = 1',
    'CSET multi_column_support = Disabled',
    'CSET number_channels = 1',
    'CSET number_paths = 1',
    'CSET optimization_goal = Area',
    'CSET output_buffer_type = Automatic',
    'CSET output_rounding_mode = Full_Precision',
    'CSET output_width = 23',
    'CSET passband_max = 0.50000000000',
    'CSET passband_min = 0',
    'CSET preference_for_other_storage = Automatic',
    'CSET quantization = Maximize_Dynamic_Range',
    'CSET rate_change_type = Integer',
    'CSET ratespecification = Sample_Period',
    'CSET registered_output = true',
    'CSET sample_frequency = 0.00100000000',
    'CSET sampleperiod = 450',
    'CSET sclr_deterministic = false',
    'CSET stopband_max = 1',
    'CSET stopband_min = 0.50000000000',
    'CSET usechan_in_adv = false',
    'CSET zero_pack_factor = 1',
    'SET device = xc3s400',
    'SET package = pq208',
    'SET speedgrade = -4',
    'CSET component_name = fr_cmplr_v5_0_3b3c9c923f48f104',
    'GENERATE',
  ];
  push(@$results, &SgGenerateCores::saveXcoSequence($instrs));
  $instrs = {
    'entity_declaration_hash' => '99cd9e13b0a83391c50fb8183397a461',
    'sourceFile' => 'hdl/xlmcode.vhd',
    'templateKeyValues' => {
      'crippled_architecture' => ' is
  component fr_cmplr_v5_0_3b3c9c923f48f104
    port(
      ce:in std_logic;
      clk:in std_logic;
      din:in std_logic_vector(7 downto 0);
      dout:out std_logic_vector(22 downto 0);
      nd:in std_logic;
      rdy:out std_logic;
      rfd:out std_logic
    );
end component;
signal dout_ps_net: std_logic_vector(22 downto 0) := (others=>\'0\');
signal rdy_ps_net: std_logic := \'0\';
signal rdy_ps_net_captured: std_logic := \'0\';
signal rdy_ps_net_or_captured_net: std_logic := \'0\';
begin
  dout_ps_net_synchronizer : entity work.synth_reg_w_init
    generic map(
        width => 23,
        init_index => 0,
        init_value => "0",
        latency => 1
    )
    port map (
        i => dout_ps_net,
        ce => ce_450,
        clr => \'0\',
        clk => clk_450, 
        o => dout
    );
  rdy_ps_net_or_captured_net <= rdy_ps_net or rdy_ps_net_captured;
rdy_ps_net_synchronizer_1 : entity work.synth_reg_w_init
    generic map(
        width => 1,
        init_index => 0,
        init_value => "0",
        latency => 1
    )
    port map (
        i(0) => rdy_ps_net_or_captured_net,
        ce => ce_450,
        clr => \'0\',
        clk => clk_450, 
        o(0) => rdy
    );
rdy_ps_net_synchronizer_2 : entity work.synth_reg_w_init
    generic map(
        width => 1,
        init_index => 0,
        init_value => "0",
        latency => 1
    )
    port map (
        i(0) => \'1\',
        ce => rdy_ps_net,
        clr => \'0\',
        clk => clk_450, 
        o(0) => rdy_ps_net_captured
    );
  fr_cmplr_v5_0_3b3c9c923f48f104_instance : fr_cmplr_v5_0_3b3c9c923f48f104
    port map(
      ce=>ce,
      clk=>clk,
      din=>din,
      dout=>dout_ps_net,
      nd=>ce_logic_450,
      rdy=>rdy_ps_net,
      rfd=>rfd
    );
end ',
      'crippled_entity' => 'is 
  port(
    ce:in std_logic;
    ce_450:in std_logic;
    ce_logic_450:in std_logic;
    clk:in std_logic;
    clk_450:in std_logic;
    clk_logic_450:in std_logic;
    din:in std_logic_vector(7 downto 0);
    dout:out std_logic_vector(22 downto 0);
    rdy:out std_logic;
    rfd:out std_logic;
    src_ce:in std_logic;
    src_clk:in std_logic
  );
end',
      'entity_name' => 'xlfir_compiler_8f30836db5fd7689324d74752f6cfaf4',
    },
  };
  push(@$results, &SgDeliverFile::deliverFile($instrs));
  local *wrapup = $Sg::{'wrapup'};
  push(@$results, &Sg::wrapup())   if (defined(&wrapup));
  local *wrapup = $SgDeliverFile::{'wrapup'};
  push(@$results, &SgDeliverFile::wrapup())   if (defined(&wrapup));
  local *wrapup = $SgGenerateCores::{'wrapup'};
  push(@$results, &SgGenerateCores::wrapup())   if (defined(&wrapup));
  use Carp qw(croak);
  $ENV{'SYSGEN'} = 'C:/Xilinx/13.2/ISE_DS/ISE/sysgen';
  open(RESULTS, '> C:/Users/mazraeh/Desktop/lab7/solution/sysgen/script_results4105965324851747111') || 
    croak 'couldn\'t open C:/Users/mazraeh/Desktop/lab7/solution/sysgen/script_results4105965324851747111';
  binmode(RESULTS);
  print RESULTS &Sg::toString($results) . "\n";
  close(RESULTS) || 
    croak 'trouble writing C:/Users/mazraeh/Desktop/lab7/solution/sysgen/script_results4105965324851747111';
};

if ($@) {
  open(RESULTS, '> C:/Users/mazraeh/Desktop/lab7/solution/sysgen/script_results4105965324851747111') || 
    croak 'couldn\'t open C:/Users/mazraeh/Desktop/lab7/solution/sysgen/script_results4105965324851747111';
  binmode(RESULTS);
  print RESULTS $@ . "\n";
  close(RESULTS) || 
    croak 'trouble writing C:/Users/mazraeh/Desktop/lab7/solution/sysgen/script_results4105965324851747111';
  exit(1);
}

exit(0);
