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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:18:26 12/18/2013 
-- Design Name: 
-- Module Name:    ps2_test - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ps2_test is
PORT (

 clk: IN STD_LOGIC;
 led: out STD_LOGIC_vector(7 downto 0);
 led_gnd :out STD_LOGIC;
 ----lcd-------
 SF_D   : out std_logic_vector(7 downto 0);
 LCD_E  : out std_logic; 
 LCD_RS : out std_logic; 
 LCD_RW : out std_logic;
 --------------------------
 KeyboardClock: IN STD_LOGIC;
 KeyboardData: IN STD_LOGIC
 
 ); 


end ps2_test;

architecture Behavioral of ps2_test is

component PS2_Ctrl IS
-- --------------------------------------
  
  port( Clk       : in  std_logic;  -- System Clock
        Reset     : in  std_logic;  -- System Reset
        PS2_Clk   : in  std_logic;  -- Keyboard Clock Line
        PS2_Data  : in  std_logic;  -- Keyboard Data Line
        DoRead    : in  std_logic;  -- From outside when reading the scan code
        Scan_Err  : out std_logic;  -- To outside : Parity or Overflow error
        Scan_DAV  : out std_logic;  -- To outside when a scan code has arrived
        Scan_Code : out std_logic_vector(7 downto 0) -- Eight bits Data Out
        );

 
 end component;
 
 signal Reset: STD_LOGIC;
 
 signal data_rdy:  STD_LOGIC;
 signal keyboard_data: std_logic_vector(7 downto 0);
 
 signal Scan_Err:  STD_LOGIC;
 signal Scan_DAV:  STD_LOGIC;
 signal DoRead:  STD_LOGIC;
 
 signal char1:std_logic_vector(7 downto 0);
signal char2:std_logic_vector(7 downto 0);
 
begin
led_gnd<='1';


u1: PS2_Ctrl 
 PORT map (

        Clk   =>clk   ,  
        Reset   =>reset   ,  
        PS2_Clk  =>KeyboardClock   ,  
        PS2_Data  => KeyboardData   , 
        DoRead   => DoRead  , 
        Scan_Err =>  Scan_Err  ,  
        Scan_DAV  => Scan_DAV  , 
        Scan_Code =>keyboard_data   
          
 ); 
 
 
 process(clk)
 variable state:integer range 0 to 2:=0;
 begin
 
 if rising_edge(clk) then
 
 case state is
 
 when 0=>

 reset<='1';
 state:=1;
 
 when 1=>
  reset<='0';
 state:=2;

 when 2=>
if Scan_DAV='1' and Scan_Err='0' then
DoRead<='1';
 led<= not keyboard_data ;
 
 if keyboard_data(7 downto 4)<x"a" then

char1<=keyboard_data(7 downto 4)+x"30";

else

char1<=keyboard_data(7 downto 4)+x"37";

end if;

if keyboard_data(3 downto 0)<x"a" then

char2<=keyboard_data(3 downto 0)+x"30";

else 

char2<=keyboard_data(3 downto 0)+x"37";
end if;

state:=0;
 
 else
 state:=2;
 DoRead<='0';

  end if;
 
 
 end case;
 



end if;
end process;
-------------
------------
--------------
process(clk)
variable cnt:integer range 0 to 2000:=0;
variable state:integer range 11 to 26:=11;

begin
if rising_edge(clk) then

-------------------
--------------------
-------lcd-------------

case state is
when 11=>

if cnt=20 then
cnt:=0;
LCD_E  <='0';
state:=12;
else
cnt:=cnt+1;
SF_D<=x"38";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=11;

end if;

when 12=>
if cnt=1600 then
state:=13;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"38";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=12;
end if;

when 13=>
if cnt=20 then
cnt:=0;
LCD_E  <='0';
state:=14;
else
SF_D<=x"0c";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=13;
cnt:=cnt+1;
end if;

when 14=>
if cnt=1600 then
state:=15;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"0c";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=14;
end if;
when 15=>

if cnt=20 then
cnt:=0;
LCD_E <='0';
state:=16;
else
SF_D<=x"01";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=15;
cnt:=cnt+1;
end if;
when 16=>
if cnt=1600 then
state:=17;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"01";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=16;
end if;

when 17=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=18;
else
SF_D<=x"06";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=17;
cnt:=cnt+1;
end if;

when 18=>
if cnt=1600 then
state:=19;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"06";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=18;
end if;

when 19=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=20;
else
SF_D<=x"80";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=19;
cnt:=cnt+1;
end if;

when 20=>


if cnt=1600 then
state:=21;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"80";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=20;
end if;








when 21=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=22;
else
SF_D<=char1;
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=21;
cnt:=cnt+1;
end if;

when 22=>
if cnt=1600 then
state:=23;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=char1;
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=22;
end if;

when 23=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=24;
else
SF_D<=x"81";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=23;
cnt:=cnt+1;
end if;

when 24=>
if cnt=1600 then
state:=25;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"81";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=24;
end if;


when 25=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=26;
else
SF_D<=char2;
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=25;
cnt:=cnt+1;
end if;

when 26=>
if cnt=1600 then
state:=19;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=char2;
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=26;
end if;

end case;
end if;
end process;


end Behavioral;

