--**********************************************************************************************
-- Product:  EZ2SUSB
-- Filename: sample1.vhd
-- Date:     08-28-2003
-- EasyFPGA
-- 905 Shell Blvd.,#202N
-- Foster City, CA 94404
-- USA
-- support@easyfpga.com
-- If this code works then it was written by Peter Bolech. If not, I don't know who wrote it.
--**********************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
Library UNISIM;
use UNISIM.vcomponents.all;


entity sample1 is port (
  -- Clock and reset --
  CLK:                  in std_logic;          -- clock 10 MHz, on-board clock
  nRESET:                in std_logic;         -- FPGA reset, on-board reset  
  -- FT245BM USB FIFO interface -

USB_D:inout std_logic_vector(7 downto 0);             --FT245BM databus
nUSB_RD:               inout std_logic;                     -- FT245BM read enable
 USB_WR:                inout std_logic;         -- FT245BM write enable
 nUSB_TXE:              in std_logic;                        -- FT245BM transmit FIFO empty flag
 nUSB_RXF:              in std_logic; 
                       -- FT245BM receive FIFO full flag
	----lcd-------
 SF_D   : out std_logic_vector(7 downto 0);
 LCD_E  : out std_logic; 
 LCD_RS : out std_logic; 
 LCD_RW : out std_logic;						  
							  
  -- LEDs
  led_gnd:out std_logic;
 LED:                   out std_logic_vector(7 downto 0)   -- on-board LEDs
 
                
  );
  end sample1;
  
--------------------------------------------  
architecture sample1_arch of sample1 is
---------------
COMPONENT clk_dcm
	PORT(
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;          
		CLKDV_OUT : OUT std_logic;
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic;
		LOCKED_OUT : OUT std_logic
		);
	END COMPONENT;
----------------------
component icon
  PORT (
    CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));

end component;


-------------------------
component ila
  PORT (
    CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
    CLK : IN STD_LOGIC;
    TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));

end component;
-----------------------
signal COUNTER:          std_logic_vector(2 downto 0);
signal COUNT_ENAB:       std_logic;
signal PRESCALER:        std_logic_vector(21 downto 0); 
signal VALUE:            std_logic_vector(21 downto 0); 
signal REG:              std_logic_vector(7 downto 0);
  
signal RST_IN:       std_logic;
signal CLK_10M:       std_logic;
signal CLKIN_IBUFG_OUT:       std_logic;
signal CLK0_OUT:       std_logic;
signal CLK_in:       std_logic;

signal CONTROL:              std_logic_vector(35 downto 0);
signal  TRIG0:              std_logic_vector(31 downto 0);
 
signal char1:std_logic_vector(7 downto 0);
signal char2:std_logic_vector(7 downto 0);
 
begin
-------------
USB_WR <= '0';
led_gnd<='1';
-----------------
chip_icon : icon
  port map (
    CONTROL0 => CONTROL);
-------------------
chip_ila : ila
  port map (
    CONTROL => CONTROL,
    CLK => CLK0_OUT,
    TRIG0 => TRIG0);

------------
Inst_clk_dcm: clk_dcm PORT MAP(
		CLKIN_IN =>CLK_in ,
		RST_IN =>RST_IN ,
		CLKDV_OUT =>CLK_10M ,
		CLKIN_IBUFG_OUT =>CLKIN_IBUFG_OUT ,
		CLK0_OUT =>CLK0_OUT ,
		LOCKED_OUT =>open 
	);



---------------
Obuf_clk : OBUF
   generic map (
      --DRIVE => 24,
      IOSTANDARD => "DEFAULT"
      )
   port map (
      O => CLK_in ,
      I => clk
    );   
---------------
--******************************************************************
USB_RD_PR: process(CLK0_OUT,nUSB_RXF)
variable state:integer range 0 to 3:=0;

begin
if(CLK0_OUT'event and CLK0_OUT = '1') then

case state is

when 0=>
nUSB_RD <= '1';
state:=1;

when 1=>
if(nUSB_RXF = '0') then 
nUSB_RD <= '0';

state:=2;
else
state:=1;

end if;

when 2=>
TRIG0(7 downto 0)<=USB_D;
led<=not USB_D;

state:=0;
if USB_D(7 downto 4)<x"a" then

char1<=USB_D(7 downto 4)+x"30";

else

char1<=USB_D(7 downto 4)+x"37";

end if;

if USB_D(3 downto 0)<x"a" then

char2<=USB_D(3 downto 0)+x"30";

else 

char2<=USB_D(3 downto 0)+x"37";
end if;







when 3=>


state:=0;
end case;
-- if(nUSB_RD = '0') then
--  nUSB_RD <= '1';
-- elsif(nUSB_RXF = '0') then 
--  nUSB_RD <= '0';
-- else
--  nUSB_RD <= '1'; 
-- end if;         
end if;
end process USB_RD_PR;
--
--
--***********************************-- 
--
--USB_WR_PR: process(CLK_10M)
--begin
--if(CLK_10M'event and CLK_10M = '1') then
--  USB_WR <= '0';
--end if;
--end process USB_WR_PR;
--
---- access to the register
----
--USB_REG_WRITE_PR: process(CLK_10M)
--begin
-- if(CLK_10M'event and CLK_10M = '1') then
--  if(nUSB_RD = '0') then
--   REG <= USB_D;
--	TRIG0(7 downto 0)<=USB_D;
--  end if;
-- end if;
-- TRIG0(7 downto 0)<= (others => 'Z');
-- USB_D <= (others => 'Z');
--end process USB_REG_WRITE_PR;
----*********************************************************************-- Walking-one
process(clk)
variable cnt:integer range 0 to 2000:=0;
variable state:integer range 11 to 26:=11;

begin
if rising_edge(clk) then

-------------------
--------------------
-------lcd-------------

case state is
when 11=>

if cnt=20 then
cnt:=0;
LCD_E  <='0';
state:=12;
else
cnt:=cnt+1;
SF_D<=x"38";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=11;

end if;

when 12=>
if cnt=1600 then
state:=13;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"38";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=12;
end if;

when 13=>
if cnt=20 then
cnt:=0;
LCD_E  <='0';
state:=14;
else
SF_D<=x"0c";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=13;
cnt:=cnt+1;
end if;

when 14=>
if cnt=1600 then
state:=15;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"0c";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=14;
end if;
when 15=>

if cnt=20 then
cnt:=0;
LCD_E <='0';
state:=16;
else
SF_D<=x"01";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=15;
cnt:=cnt+1;
end if;
when 16=>
if cnt=1600 then
state:=17;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"01";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=16;
end if;

when 17=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=18;
else
SF_D<=x"06";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=17;
cnt:=cnt+1;
end if;

when 18=>
if cnt=1600 then
state:=19;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"06";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=18;
end if;

when 19=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=20;
else
SF_D<=x"80";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=19;
cnt:=cnt+1;
end if;

when 20=>


if cnt=1600 then
state:=21;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"80";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=20;
end if;








when 21=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=22;
else
SF_D<=char1;
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=21;
cnt:=cnt+1;
end if;

when 22=>
if cnt=1600 then
state:=23;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=char1;
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=22;
end if;

when 23=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=24;
else
SF_D<=x"81";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=23;
cnt:=cnt+1;
end if;

when 24=>
if cnt=1600 then
state:=25;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=x"81";
LCD_RS <='0';
LCD_RW <='0';
LCD_E  <='1';
state:=24;
end if;


when 25=>
if cnt=20 then
cnt:=0;
LCD_E<='0';
state:=26;
else
SF_D<=char2;
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=25;
cnt:=cnt+1;
end if;

when 26=>
if cnt=1600 then
state:=19;
cnt:=0;

else
cnt:=cnt+1;
SF_D<=char2;
LCD_RS <='1';
LCD_RW <='0';
LCD_E  <='1';
state:=26;
end if;

end case;
end if;
end process;




end sample1_arch;