                        Core name: Xilinx LogiCORE IP Block Memory Generator
                        Version: 6.1
                        ISE Design Suite: 13.1 - March 2011 (O.40)

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    This document contains the following sections:

    1. Introduction
    2. New Features
    3. Supported Devices
    4. Resolved Issues
    5. Known Issues
    6. Technical Support
    7. Core Release History
    8. Legal Disclaimer

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    1. INTRODUCTION

    For the IP installation instructions for this core,
    please go to:

       www.xilinx.com/member/7_ea_sw/index.htm

    For system requirements:

       www.xilinx.com/member/7_ea_sw/EA_system_req.htm

    This file contains release notes for the Xilinx LogiCORE IP Block Memory
    Generator v6.1 solution. For the latest core updates, see the product page at:

      www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm

    2. NEW FEATURES

    - ISE 13.0.2 support
    - Support for Virtex-7 and Kintex-7 devices
    - Soft-ECC support for Virtex-6 and Spartan-6 devices
    - Support for WRITE_FIRST operating mode with SDP memory type in Spartan-6 devices

    3. SUPPORTED DEVICES

       Virtex-7
       Kintex-7

       Virtex-6 XC CXT/LXT/SXT/HXT
       Virtex-6 XQ LXT/SXT
       Virtex-6 -1L XC LXT/SXT

       Spartan-6 XC LX/LXT
       Spartan-6 XA
       Spartan-6 XQ LX/LXT
       Spartan-6 -1L XC LX

       Virtex-5 XC LX/LXT/SXT/TXT/FXT
       Virtex-5 XQ LX/ LXT/SXT/FXT

       Virtex-4 XC LX/SX/FX
       Virtex-4 XQ LX/SX/FX
       Virtex-4 XQR LX/SX/FX

       Spartan-3 XC
       Spartan-3 XA
       Spartan-3A XC 3A / 3A DSP / 3AN DSP
       Spartan-3A XA 3A / 3A DSP
       Spartan-3E XC
       Spartan-3E XA

    4. RESOLVED ISSUES

    - Spartan-6 BRAM Memory collision error
    - Version fixed : 4.3
      1. When the user selects SDP - in Virtex-6 devices
          Solution: For SDP configuration, the write_mode is set as Read_First when Common Clock is enabled otherwise the write_mode is set as Write_First
      - CR 564035

    5. KNOWN ISSUES

       The following are known issues for v6.1 of this core at time of release:

    - Virtex-6 BRAM Memory collision error

      1. When the user selects TDP (write_mode= Read First)
          Impact: User will have to consider collision Issue

    - Spartan-6 BRAM Memory collision error
      1. When the user selects TDP (write_mode= Read First)
          Impact: User will have to consider collision Issue

      Note: Refer to UG383, 'Conflict Avoidance' section while using TDP Memory, with
            Write Mode = Read First in conjunction with asynchronous clocking

    - Power estimation figures in the datasheet are preliminary.

    - Core does not generate for large memories. Depending on the
      machine the ISE CORE Generator software runs on, the maximum size of the memory that
      can be generated will vary.  For example, a Dual Pentium-4 server
      with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
      - CR 415768
      - AR 24034

    - Out-of-range address input can cause the core to generate X's on the DOUT bus
      - AR 23744

    - When the IP core is generated for Spartan-6 devices, the core should combine
      two adjacent 9k BRAMs into one 18K BRAM.
      - CR 526429

    The most recent information, including known issues, workarounds, and resolutions for
    this version is provided in the IP Release Notes User Guide located at

         www.xilinx.com/support/documentation/user_guides/xtp025.pdf

    6. TECHNICAL SUPPORT

    To obtain technical support, create a WebCase at www.xilinx.com/support.
    Questions are routed to a team with expertise using this product.

    Xilinx provides technical support for use of this product when used
    according to the guidelines described in the core documentation, and
    cannot guarantee timing, functionality, or support of this product for
    designs that do not follow specified guidelines.

    7. CORE RELEASE HISTORY

    Date        By            Version      Description
    ================================================================================
    03/01/2011  Xilinx, Inc.  6.1          AXI Support - (O.40)
    10/29/2010  Xilinx, Inc.  5.2          ISE 7 Series Monthly Snapshot - (O.28)
    10/05/2010  Xilinx, Inc.  4.3          ISE 12.3 support;
    07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support;
    04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support;
    03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue
    12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
                                           Device support; Automotive Spartan 3A
                                           DSP device support
    09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
    06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
    04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
    09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
    03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
    10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
    07/2007     Xilinx, Inc.  2.5          Revised to v2.5
    04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
    02/2007     Xilinx, Inc.  2.4          Revised to v2.4
    11/2006     Xilinx, Inc.  2.3          Revised to v2.3
    09/2006     Xilinx, Inc.  2.2          Revised to v2.2
    06/2006     Xilinx, Inc.  2.1          Revised to v2.1
    01/2006     Xilinx, Inc.  1.1          Initial release
    ================================================================================

    8. Legal Disclaimer

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