Running: C:\Xilinx\13.2\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o C:/Users/mazraeh/Desktop/fpga project/vga600/TEST_BENCH_isim_beh.exe -prj C:/Users/mazraeh/Desktop/fpga project/vga600/TEST_BENCH_beh.prj work.TEST_BENCH 
ISim O.61xd (signature 0x1cce1bb2)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Parsing VHDL file "C:/Users/mazraeh/Desktop/fpga project/vga600/dcm_clk.vhd" into library work
Parsing VHDL file "C:/Users/mazraeh/Desktop/fpga project/vga600/vga.vhd" into library work
Parsing VHDL file "C:/Users/mazraeh/Desktop/fpga project/vga600/TEST_BENCH.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package vcomponents
Compiling package numeric_std
Compiling package textio
Compiling package vital_timing
Compiling package vital_primitives
Compiling package vpkg
Compiling architecture bufg_v of entity BUFG [bufg_default]
Compiling architecture ibufg_v of entity IBUFG [\IBUFG("DONT_CARE","0",true,"DEF...]
Compiling architecture dcm_clock_divide_by_2_v of entity dcm_clock_divide_by_2 [dcm_clock_divide_by_2_default]
Compiling architecture dcm_maximum_period_check_v of entity dcm_maximum_period_check [\dcm_maximum_period_check("CLKIN...]
Compiling architecture dcm_maximum_period_check_v of entity dcm_maximum_period_check [\dcm_maximum_period_check("PSCLK...]
Compiling architecture dcm_clock_lost_v of entity dcm_clock_lost [dcm_clock_lost_default]
Compiling architecture dcm_v of entity DCM [\DCM(2.0,8,5,false,25.0,"NONE","...]
Compiling architecture behavioral of entity dcm_clk [dcm_clk_default]
Compiling architecture obuf_v of entity OBUF [\OBUF("DONT_CARE",12,"DEFAULT","...]
Compiling architecture behavioral of entity vga [vga_default]
Compiling architecture behavior of entity test_bench
Time Resolution for simulation is 1ps.
Waiting for 13 sub-compilation(s) to finish...
Compiled 31 VHDL Units
Built simulation executable C:/Users/mazraeh/Desktop/fpga project/vga600/TEST_BENCH_isim_beh.exe
Fuse Memory Usage: 47084 KB
Fuse CPU Usage: 982 ms
